SU1462359A1 - Device for tolerance monitoring of voltages - Google Patents

Abstract

The image, the subject of automation and computer technology, can be used to monitor voltages. The purpose of the invention is to increase the depth of control. The device for the tolerance control of voltages contains voltage converters

Description

one

The invention relates to automation and computational techniques and can be used to monitor stresses.

The purpose of the invention is to increase the completeness of the control; FIG. 1 is a functional block diagram of a device for tolerant stress control; 2 shows timing diagrams for his work; in fig. 3 shows an algorithm for generating signals at the outputs of the first and second comparison circuits.

The device dp of the voltage tolerance control (fig. 1) contains voltage-frequency converters 1.0-ln, the inputs of which are the device inputs, and the outputs are connected to the information inputs of the multiplexer 2, the output of which is connected to the counting input of the counting trigger 3, the output of which connected to the input of the pulse former 4, the output of which is connected to the setup input of the first register 5, the input of the accumulator 6, through the second delay element 7 to the reset input of the second counter 8, through the third delay element 9 with the counting input first 10th counter, the outputs of which are connected to the address inputs of multiplexer 2. In addition, the device contains a rator 11 pulses made of quartz; the output of which is connected: N to the first input of the first element 12, the output of which is connected to the counting input of the second counter 8, the output of the third delay element 9 is connected to the fourth delay element 13 to the installation input of the fourth register 14, the inputs of which are connected to the outputs of the first 10 counter, and exits - with address inputs

five

0

five

0

five

0

Pit 6, the outputs of which are connected to the inputs of the second 15 and third 16 registers, the installation inputs of which are connected to the output of the third delay element 9, and the outputs to the second (B, ... B, and V. .. B inputs of the first 17 and second 18 comparison circuits, respectively, the outputs and A f B of the first comparison circuit 17 are connected to the first and second inputs of the first element OR 19, respectively, and the outputs A B and - to the first 1 and the second inputs of the second element OR 20, the outputs of the first 19 and second 20 elements OR connected to the first and second inputs of the second element And 21, in addition, mouth The device contains the first 22, second 23, third 24 RS-flip-flops, one installation Z-inputs of which are connected respectively to the outputs A B of the first 17 comparison circuit, the second element 21 and A f B of the second 18 comparison circuit, and the forward outputs The device is connected to a nepBof 25 D-input, a second 26, and a third D-trigger 27. The device also includes a fifth delay element 28, the input of which is connected to the output of the third delay element 9, and the output to the input for the first 25 clock pulses, the second 26, the third 27 D-flip-flops and the input of the first delay element 29, the output to Secondly, it is connected to the reset input of the first 22, second 23 and third 24 RS flip-flops and the first 5, second 15 and third 1 registers. The device comprises a pulse generator 30, the output of which is connected to the first input of the third element I 31, the second and third inputs of which are connected respectively to the output of the first 25 and the inverse of the second

l

26 D-flip-flops, the first and second inputs of the fourth element And 32 are connected respectively to the inverse output of the second 26 and the direct output of the third 27 D-flip-flops, the outputs of the third 31 and fourth 32 And elements are connected respectively to the first and second inputs of the third element OR 33 The output of which is connected to the gate input of the decoder 34 whose outputs through the corresponding indicators 35.0-35.p are connected to the device bus, the indicator 35.p is connected to the zero output of the decoder, the indicator 35.0 to the first output, the indicator 35.1 - in To that, etc.J and the indicator 35.P-1 to the output n of the decoder, on the front panel of the device, indicators 35 are numbered and arranged in the required order, inputs 36 and 37 of the device are respectively information and input of the entry Zn and information on the upper and lower limits of variation of the monitored voltages in the accumulator, the outputs of the first register 5 are connected to the corresponding first inputs (, .. A, D first 17 and second 18 comparison circuits.

The device works as follows.

The monitored voltages and ... and (fig, 1) are fed to the corresponding inputs of the device and then to the inputs of the corresponding converters 1.0.- .. I.n voltage - the frequency that generates pulses with frequencies at its outputs

The magnitudes of the voltages and, ... and, and the increase in voltage leads to an increase in the frequency f. and, consequently, to reduce the period of the pulses generated by the converter l.i, and arriving at the i-input of the multiplexer 2 and further to the output. The output of multiplexer 2 is connected to one of the information inputs defined by a code pattern at its address input.

Suppose that a zero channel is connected to the output of multiplexer 2 and the voltage value of this channel is monitored. Converter 1.0 generates pulses with a frequency proportional to the voltage of this channel. The first pulse from the output of the converter 1.0 after

f (, ... f, are proportional to

2359

ten

15

20

35

0 counting trigger

its connection is fed to the counting input of the counting trigger 3 and sets it to the zero position (Fig. 2). The output signal of the trigger 3 is fed to the first (inverse) input of the first element And 12, allowing its operation. The pulses from the output of the generator 11 begin to flow to the counting input of the second counter 8. The second pulse from the output of converter 1.0 (coming in time to (Fig. 2), equal to the pulse period of this converter, and therefore, determined by the frequency of its operation, which the turn depends on the voltage value of the monitored channel) the counting trigger 3 is set to one and the output signal prohibits the operation of the first element 12. The pulses from the output of the generator 11 to the counting input of the counter 8 stop by to step. Thus, the higher the voltage value of the monitored channel, the higher the frequency of the pulses of the corresponding transducer, and therefore 5 the smaller the follow-up period of these pulses and, accordingly, the time during which counter 8 is enabled, and vice versa. This means that the capacity of the second meter is determined by the lower limit of the smaller of the monitored voltages, i.e. in this case, the operation of the second counter 8 will be allowed. during the longest period of time. When the second pulse from the output of converter 1.0 sets

3 in a single state, a positive voltage drop will be generated at the output of the latter, which triggers the pulse shaper 4, at the output of which a pulse appears (Fig. 2). This pulse ensures that the code stored in counter 8 (which is determined by the voltage of the monitored channel) is received in register 5 and the information from accumulator 6 is read at the address stored in register 14. In this case, this is the zero address, as it was it has been found that the voltage of the zero channel is currently monitored. I turn on-. The monitoring of monitored channels, accumulator addresses and indicators is provided by the first counter 10, the output of which is currently controlled

0

five

set zero code. In drive 6, the values of the lower and upper limits of the voltage deviation are recorded in accordance with the monitored channels, and the lower and upper limits for the corresponding channel are recorded at the same address of the accumulator 6. When reading from the accumulator, the information corresponding to the lower limit value is taken to the second register 15, and the information corresponding to the upper limit to the third register 1 The values of the allowable limits can be different and are determined by the voltage rating in the controlled channel (for example, 5 ± 5 % corresponds to i4.75 - the lower limit and 5.25 - the upper limit, 10 V + 5% corresponds to 9.5 - the lower and 10.5 - the upper limit, and 4.75; 5.25 and 9.5, 10.5). The limits from toning are recorded in the drive to the beginning of work.

The impulse, from the output of the imaging unit 4, through the time determined by the element; 7 (the time of recording information in register 5) resets the counter 8 and prepares it for further work. The Pulse from the driver's output, passing delay element 9 (reading time of information from drive 6), allows receiving the read information to registers 15 and 16 (lower and upper limit, respectively) and switches the first counter 10 to the counting input. The state of counter 10 is referred to 1, therefore, the next channel (converter 1. of the first channel) is connected to the output of multiplexer 2; The code at the Input of the address register 14 changes, and this code is accepted to the register 14 through the Time defined by element 13 (switching time of counter 10), the pulse from the output of delay element 9 selects the first input of the generator 34, to which the indicator 35.0 is connected. While all these switchings are being performed, counter code 8 (corresponding to the voltage value of the zero channel) has already been received at register 5, and information about the lower and upper limit is read from drive 6 and received at registers 15 and 16, respectively. Information from the first register is fed to the first inputs (A, AI, ..., A, ", first 17 and second 18

comparison circuits. The information from the output of register 15 is fed to the second inputs (Bj ... B) of circuit 17, and the output of register 16 is to the second inputs (B ...) of the second cxBNbi 18 comparison. In the comparison circuits, the magnitude of the voltage (information from register 5) is compared with the allowable lower 10 (information from register 15) and upper (information from register 16) limits. Let us turn to the algorithm for generating signals at the output of the first

17 and second 18 comparison circuits (FIG. 3), 15. Suppose, at time t

the first pulse from the converter was reset to the counting trigger 3 and the passage of pulses from the generator 11 through the element 12 to the counting

0 is the input of the counter 8. If the value of the monitored voltage is less than the lower permissible limit, then the pulse duration period is large and during the time interval t-t, the counter will be

5 A code is received that corresponds to point A, This code is proportional to the value of and, is accepted into register 14 and is fed to the first inputs of circuits 17

18 Comparison. The code for tolerances (Vc is the lower tolerance and Bg is the upper tolerance) from accumulator 6 is taken to registers 1 5 and 1 6 (V c - to register 15, and

Bg - on register 16). Since with an increase in the magnitude of the monitored voltage, the frequency (and therefore the period) of pulses from the output of the corresponding transducer increases, and, consequently, during a smaller space.

0 a terrible time will be allowed to work. Counter 8, this means that on - counter 8 will receive a smaller (largest) code, and vice versa. Therefore, the value of the lower limit. (in numerical expression) higher than upper Bj. As a result of the comparison of the accepted code A, (proportional to the value of the monitored voltage) with the permissible limits B and Bg received from registers 15 and 16, it can be seen (Fig. 3) that A, 7Vc, Consequently, at output A 7 In the first circuit of the 17th equation, a single signal appears, and on the remaining outputs of the circuits I7 and 18

5 comparisons are present O. In this case 11. If the counter 8 counts over time, the code A is set on it. From a comparison with the permissible limits it can be seen that L Bg, but that means 1-, P; „„. In this case, at the output of the first comparison circuit} 7 and at the output A B of the second comparison circuit 18 appears, and on the rest - O. If the counter is open for the time t-tdz, then the code means UMMH U t. e. voltage .. is within tolerance. In this case, at outputs A: B of the first 17 and A B of the second 18 comparison circuits appear 1, and on the others - O. If the counter runs for a time tt. And accepts code A, this means that, but, therefore An irmax signal 1 appears at the outputs A: B of the first 1 7 and second 18 comparison circuits. If the meter operates for a very small period of time (the frequency of the signal at the output of the converter is high, which corresponds to a large value of the monitored voltage), the code A j will be AJ Bg. In this case, the output A of the second cxei 18 of the comparison is set to 1, the remaining outputs — O. Suppose that if

, 1 MUIKC is the normal option and

controlled voltage is still normal. Depending on the size of the codes characterizing the value of eg at the input S of the second RS-flip-flop 2 if.

at the input S of the third RS-flip-flop 5 her-and ,.

and the corresponding K8 trigger will be set, .. and the other two will remain in O.

After the time determined by the delay element 28 (the response time of the comparison circuits, which have high speed, and this is one of the basic requirements for these circuits), the status information - 5 SRIs of RS-flip-flops 22-24 rewritten to the corresponding D-triggers 25-27 dp ensuring the appropriate mode of the indicator. After the time determined by element 29 of the delay, the RS-triggers will be: reset to O and ready for operation in the next cycle. „.And in state

1, trigger 23 will be set. This 25 information 1 will be rewritten into D-flip-flop 26, which will also be set to state 1. The level O from the inverse output of this trigger is fed to the corresponding inputs 30 of the third 31. and the fourth 32 elements I and G; their operation and, therefore, O will be fed to the gate input of the decoder 34 and therefore connected to the output of the decoder - J rt - x-iv; ii ™ 3in l. Descend

and the admissible limits specified by the torus are the corresponding indicator b

MIKOOSKHEMY possible nn p1ig, g, t, e- gn «M ivaiuiJ yi

chips can be extended, for which additional inputs of chips are used. The outputs and A B of the first comparison circuit 17 are connected to the inputs of the first element OR 19, and the outputs A B and the second comparison circuit 18 are connected to the inputs of the second element OR 20, which allows this option to be realized under control

det is off. Thus, if the monitored voltage is normal, the indicator does not light.

If, to the state; 1 bu40 i will be set to RS-TpHrrep; .22 and this information will be rewritten to D-flip-flop 25, which will be set to 1, and triggers 26 and 27 will remain in O. Level 1 from the direct output of triggered voltage and 4U - .U -:; - from the direct output the trigger switch kontr, olrvvmoVn: GG P 25 is supplied to the second input of the third voltage controlled voltage is normal, i.e. the condition ID,., is fulfilled, both elements OR 19 and 20 (Figs. 2 and 3) are triggered and a single signal is fed to the first and second inputs of the second element I 21, which also works. Thus, depending on the result of comparing the code characterizing the magnitude of the monitored voltage, and the codes characterizing the permissible limits,

signal 1 may occur

at the input S of the first RS flip-flop 22,

.if,. and,""

And 31, the third input of which will also be level 1 from the inverse output of flip-flop 26, and the first input of the third element 31 will be connected to the output of generator 30, and therefore, at the output of element 31, the signal will be determined by the generator signal 30, i.e. vary with the frequency of this oscillator. The signal from the 55 output of the AND 31 element, having passed the OR 33 element, arrives at the gate input of the decoder 34, i.e. the indicator connected to the corresponding output of the decoder will flicker with

at the input S of the second RS flip-flop 23, if.

at the input S of the third RS-flip-flop 5 her-and ,.

and the corresponding K8 trigger will be set, .. and the other two will remain in O.

After the time determined by the delay element 28 (the response time of the comparison circuits, which have high speed, and this is one of the basic requirements for these circuits), the status information - 5 SRIs of RS-flip-flops 22-24 rewritten to the corresponding D-triggers 25-27 dp ensuring the appropriate mode of the indicator. After the time determined by element 29 of the delay, the RS-triggers will be: reset to O and ready for operation in the next cycle. „.And in state

1, a trigger 23 will be set. This 5 information 1 will be rewritten into a D-trigger 26, which will also be set to state 1. The level O from the inverse output of this trigger is fed to the corresponding inputs 0 of the third 31. and the fourth 32 elements of I and G; their operation and, therefore, O will be supplied to the gate input of the decoder 34 and therefore connected to the output of the descrambler - J rt - x-iv; ii ™ 3in l. Descend

torus corresponding indicator b

torus corresponding indicator b

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det is off. Thus, if the monitored voltage is normal, the indicator does not light.

If RS-TpHrrep; .22 is set to the details state and this information will be rewritten to D-flip-flop 25, which will be set to 1, and flip-flops 26 and 27 will remain in O. Level 1 from the forward trigger output:; - from the direct output, the trigger 25 is supplied to the second input of the third 25 is fed to the second input of the third element AND 31, the third input of which will also be level 1 from the inverse output of the trigger 26, and the first input of the third element And 31 will be connected to the output of the generator 30, and therefore, at the output of the element 31, the signal will be determined by the signal of the generator 30, i.e. vary with the frequency of this generator. The signal from the output of the AND 31 element, having passed the OR 33 element, arrives at the gate input of the decoder 34, i.e. the indicator connected to the corresponding output of the decoder will blink at a generator frequency of 30, which is chosen so that it is convenient to observe the flashing of the indicator. The operation of the AND 32 element is blocked by the level O from the output of the trigger 27, which is located in O. If U. THEN is set to 1 trigger 4 and the information from it is also overwritten by trigger 27, which also sets |: 1. The output of the rigger 27 is supplied to the second input of the jieTBepToro element E 32, on the first floor of which also. there will be a level il from the inverse output of the trigger 26, which together with the trigger 25 remain in O. The signal from the output of the trigger 5 blocks the operation of the element 31. Lemme And 32 will work, and the signal 11 from its output, pass element

| OR 33, will go to the input of the decoder, $ 4, and the indicator connected to its OUTPUT will be lit. : It was noted that by the time when | 1 the comparison of codes began (i.e. the values of voltage and tolerances) applied to the first 5, second 15 and third 16 registers, counter 10 had switched, which connects the next channel to the multiplexer output, selects the next storage address and switches the decoder 34, but the indicators 35.0-35.p are connected in such a way that when the voltage of the 1st cantileat is monitored (i.e., counter 8, and then compare this code with tolerance codes), at this point to the output The decoder is connected to a (1-1) -th indicator, which signals the results of monitoring the magnitude of the voltage of the previous; tcypiero channel.

When counter 10 is switched, the next channel is connected; l (the corresponding converter) and trigger pulse 2 is reset from the converter output and counter 8, which has been prepared for operation, starts to work, then the next code from counter 8 is compared with the codes tolerances and display of voltage control results of the previous channel.

The device provides a serial connection of monitored channels and an indication of the results of the control. Counter 10 is circular, i.e.,: having calculated to the maximum value.

0 5 0

5 0 o

g

five

returns to its original state and counts again.

In case the monitored voltages or tolerances of the monitored voltages (connected to control new power sources) at least in one of the channels have changed, the information on new tolerances is recorded in the drive, which can be done, for example, with a photo reader. Similarly, the speed of changing information on tolerances of monitored voltages in any of the channels or in all channels at the same time, makes it easy to operate the device, and the ability to control different voltages with different tolerances in each of the channels significantly increases the depth of control in the proposed device compared to the known, which allows to control the voltage of one nominal -. .with . Same tolerances in each channel.

One of the main indicators of the effectiveness of the known and proposed devices is the number of voltage voltages of various ratings that can be monitored.

For the known device, the value in the proposed device, the value of n is determined by the size of 1 of the counter 10 and is limited by the value. Thus, the invention is 2 times greater than the known device for tolerance control.

 about rm y l, and the invention n. and

Device for tolerance control of voltages, containing voltage converter - frequency, first delay, multiplexer, counting trigger, indicators, pulse generator, first and second counters, first and second RS-triggers, first and second 1) triggers decoder and pulse generator, Whr. - voltage transducer voltage – frequency are the device inputs, and the outputs are connected to the corresponding information inputs of the multiplexer, the output connected to the counting input of the counting trigger, the outputs of the first counter are connected to the corresponding address inputs of the decoder, the output of the first element delay connected to the reset inputs of the first and second RS-flip-flops, the outputs connected to the corresponding information inputs of the first and second D-flip-flops, you ode decoder connected through soot- vetstvuyup1ie indicators corresponding to the information device outputs

so-called

that, in order to increase the completeness of the control, the first to fourth elements AND, the first to the third OR elements, the second; the fifth delay elements, the first to the fourth registers, the pulse shaper, the drive, the first and the second comparison circuit, the third RS-trigger and the third D-trigger, the outputs of the pulse generator and the counting

the trigger is connected respectively to the direct inverting inputs of the first element I, the output of the second counter connected to the counting input, the output of the counting trigger is connected to Efxo, the pulse former, the output through the second delay element connected to the reset input of the second counter and directly connected to the setup input of the first register country, with the input of the third delay element and the read input of the storage device, the output of the third delay element connected to the counting input

They are connected to the address inputs of the accumulator, the information entries of which are the corresponding inputs of the device, and the outputs are respectively connected to the information memory inputs of the third third registers, the output of the first delay element is connected to the first, second and third registers and the third RS -trigger output connected to the input of the third B-trigger, output More than the first comparison circuit, output of the second element OR and output Less than the second circuit, the comparison is connected to the inputs of the installation in 1 RS-trigger with the first Third and third, respectively, the outputs are connected to the first groups of the first and second comparison circuits, the second groups of inputs connected to the outputs of the first register, the outputs Equal and Less than the first comparison circuit are connected to the corresponding inputs of the first LC element, the outputs More and Equally the second comparison circuit is connected to the corresponding inputs of the second OR element, the output of which and the output of the first element OR are connected to the corresponding inputs of the second element AND, the outputs of the first D-flip-flop and the gene Ator pulse connected to the first

the first counter, with the installation input and the second inputs of the third element

On the second and third registers, through the fourth delay element - with the setup input of the fourth register, through the fifth delay element - with the D-flip-flop synchronous inputs from first to third, the output of the fifth delay element is connected to the input of the first delay element, the outputs

the first counter is connected with the corresponding

the corresponding information inputs j of the encoder, the fourth register, the outputs of which are, the output of the second D-flip-flop is connected to the third input of the third element I and to the first input of the fourth element I, the second input of which is connected with the output of the third D-flip-flop and the output from the first the input of the second element OR, the second input connected to the output of the third element and the output to the gate input d

They are connected to the address inputs of the accumulator, the information and recording inputs of which are the corresponding inputs of the device, and the outputs are respectively connected to groups of information inputs of the second and third registers, the output of the first delay element is connected to the reset inputs of the first, second and third registers and the third RS- the trigger, the output connected to the input of the third B trigger, the output More than the first comparison circuit, the output of the second element OR, and the output Less than the second circuit, the comparison is connected to the installation inputs in 1 The first to third RS triggers respectively, the outputs of the second and third registers are connected respectively to the first groups of the first and second comparison circuits, the second groups of inputs connected to the outputs of the first register, the Equals and Less than the first comparison circuits are connected to the corresponding inputs of the first CID element, the outputs More and Equal to the second comparison circuit are connected to the corresponding inputs of the second element OR, the output of which and the output of the first element OR are connected to the corresponding inputs of the second element AND, the output The first D-flip-flop and pulse generator are connected to the first

and the second inputs of the third element

and the second inputs of the third element

„

encoder,

And, the output of the second D-flip-flop is connected to the third input of the third element And to the first input of the fourth element And, the second input of which is connected to the output of the third D-flip-flop, and the output to the first input of the second element OR, the second input connected to the output of the third element And, and the exit - to the gate entrance de

Claims (1)

Form l, and the invention of n. and I Device for tolerances of voltage control, containing voltage-frequency converter, first delay element, multiplexer, counting trigger, indicators, pulse generator, first and second counters, first and second RS-flip-flops, first and second D-flip-flops, decoder and generator pulses, input · ^{1 of the} converters · voltage frequency are the inputs of the device, and the outputs are connected to the corresponding information inputs of the multiplexer, the output connected to the counting input of the counting trigger, the outputs of the first counter connected to the corresponding address inputs of the multiplexer and to the corresponding information inputs of the decoder, the output is primary 1 1 1 2 of the second delay element is connected to the reset inputs of the first and second RS flip-flops, the outputs are connected to the corresponding information inputs of the first and second D-flip-flops, the decoder outputs are connected through the corresponding indicators to the corresponding information outputs of the device, characterized in that, in order to increase the control completeness, from the first to the fourth elements AND, from the first to the third elements OR, from: the second to the fifth delay elements, from the first to the fourth registers, the pulse shaper, are introduced into the device opitel, first and second comparison circuit, the third RStrigger and third D-flip-flop, the outputs of the pulse generator and counting trigger 20 are connected respectively to the inverting inputs of the first straight. And element, by the output of the second counter connected to the counting input, the output of the counting trigger is connected to the Rho-25 house of the pulse shaper, through the second delay element connected to the reset input of the second counter and directly connected to the installation input of the first register, with the input of the third element delays and with the drive read input, the output of the third delay element is connected to the counting input of the first counter, with the installation inputs of the second and third registers _? through the fourth delay element with the installation input of the fourth register, through the fifth delay element with the sync inputs of the D-flip-flops from dd first to third, the output of the fifth delay element is connected to the input of the first delay element, the outputs of the first counter are connected to the corresponding information inputs of the fourth register, the outputs of which connected to the address inputs of the drive, the information inputs and records of which are the corresponding inputs of the device, and the outputs are respectively connected · to the information groups inputs of the second and third registers, the output of the first delay element is connected to the reset inputs of the first, second and third registers and the third RS-trigger, the output connected to the input of the third О ^ trigger, the output is More than the first comparison circuit, the output of the second OR element and the output Less than the second circuit comparisons are connected to the installation inputs in 1 RS-flip-flops from the first to third, respectively, the outputs of the second and third registers are connected respectively to the first groups of the first and second comparison circuits, the second groups of inputs connected to the outputs of the first register, the outputs Equal and Less than the first comparison circuit are connected to the corresponding inputs of the first OR element, the outputs More and Equal of the second comparison circuit are connected to the corresponding inputs of the second OR element, the output of which and the output of the first OR element are connected to the corresponding inputs of the second AND element, the outputs of the first D-trigger and the pulse generator are connected to the first and second inputs of the third element And, the output of the second D-trigger is connected to the third input of the third element And to the first input of the fourth And element, the second input of which is connected to the output of the third D-trigger, and the output - with the first input of the second OR element, the second input connected to the output of the third And element, and the output - to the gate input of the decoder.