SU1721698A1 - Phase interleaving control unit - Google Patents

Abstract

The invention relates to electrical engineering and can be used in electrical installations that require a certain order of phase alternation of a three-phase AC network. The purpose of the invention is the elimination of spontaneous operation of the device after eliminating the emergency mode of the network. The operation of the device is possible only after closing the controlled key 13, as a result of which the output pulse of the driver 3 of the pulses arrives at the second input of the element OR 8. When a pulse appears at the output of the driver of the pulse 1, a pulse appears at the output of the element 4, which ensures the appearance of pulses at the outputs of the elements And 5-7, arriving at the inputs of the element OR 12, at the output of which a signal of the logical unit is formed, corresponding to the operation of the device. 3 il.

Description

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Claims (1)

Claim A device for controlling phase rotation, containing the first, second and third pulse shapers with inputs for connecting to the corresponding phases of the monitored network, the first, second and third AND elements, the first inputs of which are connected to the outputs of the corresponding pulse shapers, the first, second and third OR elements, connected by the first inputs to the outputs of the corresponding elements And, and the outputs to the second inputs of the first, second and third elements, respectively, the fourth element And, connected by the first input to the output of the first AND element, and the output - to the first input of the fourth OR element, connected by the output to the second input of the fourth AND element, the output of which is also connected to the first input of the fifth OR element, characterized in that, in order to exclude spontaneous operation of the device after eliminating the network emergency mode , a controlled key is additionally introduced, and the first OR element is made with three inputs, while the controlled key is connected between the output of the third pulse shaper and the second input of the first OR element, the third input to which is connected to the output of the third AND element, also connected to the second inputs of the fourth and fifth OR elements, the third input of the last of which is connected to the output of the second AND element, also connected to the second input of the third OR element, and the output of the first AND element is connected to the second input second element OR. ft 1 ...... 1 l ~ 1t 16_______I I I I I ----------- 11 I I I ----- 1 I ---- 18 I ----— Ίl ~ I 19 I --------- 1_________________II 20 ______________________ I -------------- 1 I ---------- 21 _______________________________ l ~~ '1 22 \ ___________________________ l ~ t Fie. 2 26 ί -ί ______ [Σ :: = 1t V) 1 I__________________I ... I _______: _________ I ---------- 25 ~ --- 1 I I ______ r ~ =. J_ 26 ------ 1 l ~ ......— I I1 27 ___________CZL_________ ΓΊ ______ 28 ---------------------------------------- 29 ----------------------------------------------- _: - --------------- JO ------------------------- FIG