SU1339899A1 - Decoder checking device - Google Patents

Abstract

The invention relates to computing and can be used in diagnostic equipment. The purpose of the invention is to simplify the device. A device having information inputs 1-11 contains a threshold element 13, an element NOT 18, a group of elements AND 20, 21, elements OR 22-24, triggers 25, 26 and elements AND 27, 28. The introduction of element NO 19 and elements 14- 17, the delay with corresponding connections provides a simpler implementation of the device. 3 ill., 1 tab. (L oo CO-CO 00 (G with Fig /

Description

The invention relates to computing and can be used in diagnostic equipment and control equipment.

The purpose of the invention is to simplify the device.

Figure 1 shows the functional diagram of the device; 2 and 3 are timing charts of its operation.

The device for controlling the decoders contains the first information inputs 1-8, the second, third and fourth information inputs 9-11, the decoder 12, the threshold element 13, the first to the fourth delay elements 14-17, the first and second elements 18 and 19 , the first group of elements And 20, the second group of elements And 21, the first, second and third elements OR 22-24, the first and second triggers 25 and 26, the first and second elements And 27 and 28 and the output 29 of the device.

The time diagrams (Figures 2 and 3) indicate the signals: a, 5, at the outputs of the second and first elements, OR 23 and 22; 8 - at the second information input 9, d - at the outputs of the first and second elements 14 and 15 of the delay e, w - at the outputs of the second and first triggers 26 and 25; output 29 of the device.

The operation of the device is explained in the table.

The device for controlling the JTOpoB decrypt works as follows,.

In the initial state, the triggers 25 and 26 are set to the zero state (low potential at the forward output). Code combinations are input to the decoder 12 at an arbitrary frequency (period T). The sequence of code combinations is chosen so that the outputs of the decoder 12 appear signals in a predetermined sequence (for example, in order of increasing from first to eighth).

The time delay of the signal by each element is 16 and 17 is equal to t / 2 (where C is the duration of the input signal). The delay time of the element 15 is equal to the period T of the change of the code combination at the input of the decoder. The delay time of element 14 is T / 2.

When applying to the inputs of the decoder 12 of the first input combination, the signal from input 9 sets the triggers 25 and

26 into one state and simultaneously delayed by a delay time T / 2 by delay element 14. The first input combination (combination 001 at the inputs of the decoder 12) corresponds to a combination of 10,000,000 at the outputs of the monitored decoder 12. Input 1 shows an information signal that goes to the first input of the fourth element And 21 of the second group, at the second and third input of which there is a logical 1 signal from the outputs of the HE elements 18 and 19. Passing through the fourth element and 21 of the second group, an information signal appears at the output of the OR element 23 and the falling edge returns the trigger 26 to the initial state.

Through time T / 2 at the output of the element

14 delay appears a logical signal 1, which interrogates the direct output of the trigger 26 on the element And 28. In addition, the same signal of logical 1 enters the input of the delay element 15 and is delayed by it for time T.

After a time equal to the period T of the change of code combinations, the second code combination enters the inputs of the decoder 12. The signal from input 10 arrives at delay element 16 and is delayed by it for time t / 2. The second input combination (the combination 010 at the inputs of the decoder 12) corresponds to the combination 01000000 at the outputs of the monitored decoder 12. At the input 2 of the device, an information signal is extracted that goes to the first input of the first element AND 20 of the first group, the second and third inputs have a logical signal 1 from the output of the delay element 16 and the NOT element 19. Passing through the first element AND 20 of the first group, an information signal appears at the output of the element OR 22 and the falling edge returns the trigger 25 to its initial state.

After a time T / 2, a logical 1 signal appears at the output of the element

15 delays that interrogate the direct output of trigger 25 on the element

And 27 „

If the decoder 12 is healthy, i.e. the signal at the output of the decoder 12 corresponds to the input code combination, then the device for controlling the decoder 12 works in the same way as described.

When various types of malfunctions occur in the controlled decoder 12 (for example, when there is no output bus in the presence of an input code combination or when an unnecessary bus is triggered, i.e., the output signal of the input code combination does not match) the signals at the outputs of the And 20 elements of the first group and the AND 21 elements of the second group do not match, therefore the triggers 25 and 26 do not return to the initial state. In this case, at the inputs of element 28, the signal from the output of trigger 26 coincides with the signal that appears at the output of element .14 of the delay with a 2T period, or at the inputs of element 27, the signal from the output of trigger 25 coincides with the signal Appears at the output of delay element 15 with a period of 2T. At the output of the element AND 28 or at the output of the element AND 27, a signal appears which, having passed through the element OR 24, signals itself in the operation of the decoder 12.

In the case when, at the output of the decoder 12, the required bus is excited by an unnecessary, at the output of the threshold element 13, which is set to the threshold, exceeding the nominal value of the output potential, a fault signal appears that passes through the element OR 24 to the output 29 of the device.

Thus, the proposed device for controlling the decoders reveals all types of failures and failures in the controlled decoder and has a simpler implementation than the known

Claims (1)

Invention Formula A device for controlling decoders containing the first and second groups of elements AND, the outputs of elements AND of the first group are connected to the inputs of the first element OR, the second element OR, the first element NOT, the elements AND, triggers and the threshold element, output which is connected to the first input of the third element OR, the inputs of the threshold element are the first information inputs of the device, characterized in that, in order to simplify the device, the second element NOT and the delay elements, the input of the first delay element and the S inputs of the first and second the triggers are combined and are the second information input of the device, the output of the first delay element through the second delay element and directly connected to the first inputs of the first and second elements respectively, the first The strokes of the AND elements of the first and second groups are connected respectively to the even and odd first information inputs of the device, the outputs of the AND elements of the second group are connected to the inputs of the second OR element, the inputs of the third and fourth delay elements are respectively the third 1-5 and fourth information inputs of the device, the third output the delay element is connected to the input of the first element is NOT and the second inputs of the second and fourth elements are And the first and first and third elements And the second group, the output of the first element is NOT yuchen to the input of the first and third elements of the first group and the second and fourth elements of the second group, the output of the fourth delay element is connected to the input of the second element NOT and the third inputs of the second and third elements of the first group and the first and second elements of the second group , the output of the second element is NOT connected to the third inputs of the first and fourth elements of AND of the first group and the third and fourth elements of the second group, the outputs of the first and second elements of OR are connected to the R-inputs of the same trigger, direct you the moves of which are connected to the second inputs of like elements and the outputs of which are connected to the second and third inputs of the third OR element, the output of which is the output of the device. Signals for information entrances 9 10 I 11 one ABOUT one ABOUT one ABOUT 1 o about 1 1 about about 1 1 about about about about one one one about Signals on vkodak elements 27 28 J 24 one about one about one about one about oh oh oh oh oh oh oh oh oh oh oh oh oh oh oh oh oh oh CJ vc "i Editor O. Yurkovetska Order 4351/56 Circulation 901 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 "about Compiled by O. Revinsky Tehred M. Khodanich Proofreader V. But ha