SU1279056A1 - Device for protection against chattering - Google Patents

Abstract

The invention relates to a pulse technique. The goal is to increase operational reliability by simplifying the device. The device for protection against bounce contains the majority element 1, the input and output bus 2,3. The goal is achieved by introducing an inverter and a delay element 5 (in the simplest case, an integrating RC-chain), which delays the inverted output signal by a time which is known to be longer than the transition time during the formation of the front and the cutoff of the signal contacts when switching. The device can be used in processing and forming systems with pulse signals. 2 Il. "

Description

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The invention relates to a pulse technique and can be used in systems for processing and generating pulse signals.

The purpose of the invention is to increase the reliability of operation by simplifying the device.

FIG. 1 is an electrical functional diagram of the device in FIG. 2 - time diagrams that show his work.

The chatter protection device contains the majority element 1 whose first input is connected to the input bus 2, the second input to its output, the output bus 3 and the input of the inverter 4, the third input to the output of the delay element 5, whose input is connected to the output of the inverter.

The delay element 5 (in the simplest case, the integrating RC-treadmill) delays the inverted output signal by a time that is known to be longer than the transient time when the front of the cutoff signal Ir is formed, for example, the time of mechanical contact bounce when switching.

U (the three works as follows.

Suppose that in the initial state on the input bus 2 and the output bus 3 there is a high potential, and at the output of the inverter 4 and the delay element 5 there is a low potential. Thus, at the second input of the majority element 1 there is a high potential, at the third input there is a low potential, and at the first input and output of the majority element 1, i.e. on the output bus 3 high potential (Fig. 2, t t).

When the potential at the input bus 2 (Fig. 2, a) is first changed from a high level to a low one at the output of the majority element 1 (Fig. 2, d) and its first input, a low potential is established. At the third input of the majority element 1 there remains a low potential (Fig. 2, B), which holds the low potential of the output of the majority element 1 for a time determined by the delay element 5. In this case, the interference that occurs on the input bus 2, i.e. at the second input of the majority element 1, do not cause a change in its output state. At time t, (FIG

2.6) at the output of the delay element 5, i.e. at the third input of the majority element 1 a high potential appears which does not change the state

the output of the majority element 1, as at the input bus 2 at the same time there is a low potential (figure 2, a).

When first changing the potential on the input bus 2 from a low level

a high potential is set to high at the output of the majority element 1 and its first input, a high potential remains at the third input of the majority element 1 (Fig. 2,

5, j), which holds the high potential of the output of the majority element 1 for a time determined by the delay element 5 (Fig. 2). In this case, the interference that occurs on the bus line 2, i.e. at the second input of the majority element 1, do not cause a change in the output state of the majority element 1. At time t, (Fig. 2.6), the output of delay element 5, i.e. At the third input of the majority element, a low potential appears that does not change the exit states of the majority element 1, since there is a high potential on the input bus 2 (Fig. 2, a, t. t ,,).

Thus, at the output of the proposed bounce protection device, an impulse is formed, on whose fronts there are no oscillatory transients, provided that the delay time of the delay element exceeds the transient time in the input signal.

Claims (1)

Invention Formula Bounce protection device, CQ45 holding the input bus connected to the first input of the majority element, the output of which is connected to the output bus, characterized in that, in order to increase its reliability by simplifying, an inverter and a delay element are inserted into it that is connected with the second input of the majority element and the input with the output of the inverter, the input 55 of which is connected to the output width and the third input of the majority element. but G. I I . year to :: l fpuz.2