RU1804676C - Synchronization device - Google Patents

Abstract

Usage: in electrical engineering when synchronizing synchronous generators of mobile sources of increased frequency. Essence: the synchronized voltages Ui and LJ2 through the formers of rectangular pulses 15 and 16 are fed to the first inputs of the elements And 22 and 23, the second inputs of which are pulses from a pulse generator of a stable frequency. From the outputs of the elements And 22 and 23, the signal goes to the counters, the outputs of which are connected to the inputs of the element And 21, the other two inputs of which are connected to the shapers of short pulses 19 and 20, the signals at the outputs of which occur at the end of the positive voltage periods Ui and U2. If all four signals coincide on the And 21 element, a signal to turn on the switch appears. 2 ill.

Description

The invention relates to electrical engineering and can be used to synchronize synchronous generators of mobile power sources of increased frequency.

The aim of the invention is to increase the reliability of synchronization.

Figure 1 presents a diagram of a synchronization device; figure 2 - plot signals at the main points of the circuit.

The synchronization device contains buses 1 and 2 of the generators connected by power contacts 3-5 of the circuit breaker. In parallel to contacts 3-5, respectively, the first, second and third electronic keys 6-8 are included. The fourth electronic key 9 is connected in series with the coil 10 of the automatic: switch. The control inputs of the keys 6-8 through the opening block contact 11, and the key 9 are directly connected to the output of the trigger 12. The same phases of the buses 1 and 2 through the valves 13 and 14 are connected to the inputs of the formers 15 and 16 of rectangular pulses. The output of the first rectangular pulse generator 15 is connected through the first practical element HE 17 to the input of the first short pulse generator 19, the output of which is connected to the first input of the first logic element And 21 and the reset input of the first pulse counter 24, The output of the second rectangular pulse generator 16 is connected through a second logic element NOT 18 to the input of the second short-pulse driver 20, the output of which is connected to the second input of the first logical element And 21 and the reset input of the second pulse counter at 25. The logic elements And 22 and 23 are connected by the outputs to the counting inputs of the pulse counters and 25, respectively, which are connected by the output bits to the corresponding bits of the inputs of the decoders 26 and 27. The stable frequency pulse generator 28 is connected by the output to the second inputs of the logic elements And 22 and 23, the first inputs of which are connected respectively to the outputs of the rectangular pulse shapers 15 and 16. A group of connected outputs of the decoder 26, corresponding to the range of frequencies acceptable for synchronization, is connected to the third input of the logic element And 21, to the fourth input. Which is connected to the same group of outputs of the decoder 27. The output of the first logic element And is connected to a single input of the trigger 12.

The synchronization device operates as follows.

Let the voltage frequencies of the generators be not equal to fi fz. When negative half-waves of voltages Ui and U2 appear, there are no signals at the output of the rectifier pulses 15 and 16. The inputs of the logic elements NOT 1.7 and 18 are low, and at their outputs appears

signal, the duration of which corresponds to half the period. The signals from the output of the logic elements NOT 17 and 18 are fed to the inputs of the shapers of short pulses 19 and 20. Short pulses from the outputs

shapers 19 and 20 are respectively supplied to the first and second inputs of the logic element And 21 and to the reset inputs of counters 24 and 25. In this case, zero codes appear at the outputs of counters 24 and 25, and a signal at zero inputs of decoders 26 and 27. There are no signals at the third and fourth inputs of the And 21 element, and it is closed,

When a positive half-wave appears from the outputs of the formers of rectangular pulses 15 and 16, the pulses arrive at the first inputs of the logic elements And 22 and 23, the second inputs of which receive pulses from the generator of the jupuls of a stable frequency 28. Since the duration of pulses Xs 15 and 16, corresponds to half the period of the corresponding sinusoidal voltage, then the Xe pulses from

a stable frequency pulse generator 28 passes through the logic elements And 22 and 23 to the counting inputs of the counters 24 and 25 during this period of time - signals Hu and Xn. At the output of counters 24 and 25

binary codes are generated which are fed to the inputs of the decoders 26 and 27. As the code increases by one, the signal goes from the previous to the subsequent output of the decoder, and. if the code reaches.

of the value corresponding to the nominal frequency, taking into account the permissible frequency deviation, then the signals Xia, Xia are received at the third and fourth inputs of the And 21 element. If the voltage phases Ui and U2 do not coincide at the time of the appearance of the negative half-wave, when signals X and Xb appear. then the signals of Xia and Xia will arrive at the third and fourth inputs of the And 21 element at different times and the And 21 element will not work.

The necessary pulse duration Chi from the output of the element And 21, which ensures the triggering of the trigger 12, is created due to the intrinsic response time of the counter and decoder.

If the frequencies of the generators coincide (with an acceptable error) and the phases by the time the signals X and Xb appear, the signals Xi2 and Xi3 will be on the third and fourth inputs of the And 21 element, and it will open. The signal from the output of the And 21 element puts the trigger 12 in a state in which a signal appears at its output, coming through pin 11 to the keys 6-8, which, when triggered, turn on the generators for parallel operation at time ti.

At the same time, the signal from the output of the trigger 12 opens the key 9 and supplies the voltage to the coil 10 of the circuit breaker, which at time ta closes its contacts 3-5 with a delay due to the response time tcpae. The contact 11 of the circuit breaker opens the key control circuit 6-8, and they disconnect.

; compare with the invention

A synchronization device containing the first and second rectangular pulse shapers, the inputs of which are connected to the bus phases of the first and second generators of the same name, connected by power contacts of the circuit breaker, the first and second short pulse shapers, the first, second and third logic gates And and a trigger different the fact that, in order to increase the reliability of synchronization, it is equipped with two logical elements NOT, four electronic keys, two counters, two decoders, a generator and pulses of a stable frequency, and the first logical element And made four-input, the output of the pulse generator is connected to the second inputs of the third and second elements And, the first inputs of which are connected respectively with the outputs of the second and first rectangular pulse shapers, the output of the first

a rectangular pulse shaper is connected through the first logic element NOT to the input of the first short pulse shaper, the output of which is connected to the first input of the first logical element AND and the reset input of the first counter connected by the output bits to the corresponding bits of the inputs of the first decoder, and the counting input - with the output of the second logical element I. the output of the second driver of rectangular pulses through the second logic element is NOT connected to the input of the second driver of short pulses, the output for which it is connected to the second input of the first logical element And and the reset input of the second counter connected by the counting input to the output of the third logical element And, and the output bits to the corresponding input bits of the second decoder, the third and

the fourth inputs of the first logical element And are connected to a group of connected outputs corresponding to the range of frequencies allowed for synchronization, respectively, of the first and second decoders.

the output of the first logical element AND is connected to a single input of the trigger, the output of which is connected to the control input of the fourth electronic key connected in series with the switching coil of the automatic switch, through the opening block contact of which the output of the trigger is connected to the control inputs of the first, second and third electronic keys, connected in parallel with the corresponding power contacts of the circuit breaker.

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