RU2084073C1 - Parallel inverter control device - Google Patents

Abstract

FIELD: DC-to-AC industrial-frequency inverters. SUBSTANCE: device is universal module capable of operating both in off-line mode and with external ac control signal of desired frequency. Device has master oscillator, normalized-length delay shaper, pulse distributor, multiplexor, first and second phase-shifting units, switching unit, first, second, and third pulse shapers, inverter, decoder, comparison circuit, and normalized pulse number delay shaper. EFFECT: provision for eliminating inverter transformer and load saturation due to gradual transfer in each half-cycle from shorter to longer duration up to rated half-cycle length, that is, up to rated ac voltage frequency; provision for operating into inductive load. 3 dwg

Description

 The invention relates to electrical engineering and can be used to build power systems, mainly with the conversion of direct current to alternating industrial frequency.

A device for controlling an electrical converter with surge protection, comprising a master oscillator, a pulse counter, a decoder, a block of control pulse shapers, an inverter and a phase shifter [1]
This device cannot operate with an external AC control signal in order to obtain the in-phase output voltage of the converter and cannot operate at an AC frequency of industrial frequency.

Of the known devices, the closest is a parallel inverter control device containing a master oscillator, a first phase-shifting unit, a first pulse shaper, the output of which is connected to the inverter, the first element NOT, a delayed driver of normalized duration, the first and second control inputs of the device [2]
The disadvantage of this device is the inability to use it at an industrial frequency of alternating current of 50 Hz, as well as when working on an inductive load with low cosΦ.

 The objective of the invention is to provide the possibility of using a DC-DC to AC low frequency (50 Hz or less) when working on an inductive load.

 The task is implemented as follows.

 A parallel inverter control device containing a master oscillator, a first phase-shifting unit, a first pulse shaper whose output is connected to the inverter, a first element NOT, a delayed shaper of normalized duration, the first and second control inputs of the device, is equipped with a pulse distributor, the outputs of which are connected to the information inputs of the multiplexer the output of which through the second pulse shaper is connected to the input of the first phase-shifting unit, the first installation input of the distribution Pulsing pulses and the counting input of the decoder, the outputs of which are connected to the inputs of the matching circuit and the address inputs of the multiplexer, it is also equipped with a switching unit, a third pulse shaper, a second phase shifter, the output of which is connected to the counting input of the delay shaper of the normalized number of pulses, the first control input of the device through the second element is NOT connected to the second input of the installation of the pulse distributor and the installation input of the decoder, the blocking input of which is connected to the output of the circuit with flow, the counting input of the pulse distributor is connected to the output of the master oscillator and to the counting input of the delay driver of normalized duration, the first control input of the device is connected to the first control input of the switching unit and the installation input of the delay driver of the normalized number of pulses, the outputs of the first and second phase-shifting nodes are connected, respectively, to the first and second signal inputs of the switching unit, the output of which is connected to the first pulse shaper, and the second control in od connected to the output and the input of the delay lock shaper normalized durations as well as driver input delay lock normalized number of pulses and the second control input is connected via a third pulse generator to the input node of the second phase shifter.

 A comparative analysis of the claimed invention with the closest analogue revealed the differences indicated in the characterizing part of the claims, which indicates the satisfaction of the invention patentability condition "novelty".

 A patent search in this technical field did not reveal technical solutions having features matching the distinguishing features of the invention and providing the indicated technical result, which indicates that the invention satisfies the patentability condition "inventive step".

 The proposed device is a universal module that can operate both in stand-alone mode and in the mode with an external AC control signal of the required frequency.

 Functional rebuilding of the device from stand-alone mode to a mode with an external control signal is performed by changing the logic level at the first control input of the device.

 The device eliminates the saturation of the inverter transformers and the load due to the gradual transition in each half-cycle of the alternating current from a shorter duration to a longer half to the nominal duration of the half-cycle, i.e., the rated frequency of the alternating current voltage.

 Figure 1 shows the functional diagram of the device; figure 2, 3 is a timing diagram of stresses explaining its operation.

 The parallel inverter control device contains a master oscillator 1, the output of which is connected to the counting inputs of a delay driver of normalized duration 2 and pulse distributors 3, the outputs of which are connected to the information inputs of multiplexer 4, the first phase-shifting unit 5, the output of which is connected to the first signal input of the switching unit 6, the first control input of which is connected to the first control input of the device, and the output of which through the first pulse shaper 7 is connected to the inverter 8, the output the multiplexer 4 through the second pulse shaper 9 is connected to the counting input of the decoder 10, the outputs of which are connected to the address inputs of the multiplexer 4 and to the inputs of the matching circuit 11, the output of which is connected to the lock input of the decoder 10, the second control input of the device through the third pulse shaper 12 is connected to the input the second phase-shifting unit 13, the output of which is connected to the second signal input of the switching unit 6 and to the counting input of the delay driver of the normalized number of pulses 14, the installation input of which the second is connected to the first control input of the device, and the output through the first element is NOT 15 connected to the installation input of the delay driver of normalized duration 2, the output of which is connected to the second control input of the switching unit 6 and the lock inputs of the delay driver of the normalized duration 2 and the delay driver of the normalized number of pulses 14 , the first control input of the device through the second element is NOT 16 connected to the input of the decoder 10 and the second input of the pulse distributor 3, the first input d installation which is connected to the output of the second pulse shaper 9.

 The proposed device operates as follows.

 In the absence of signals at the 1 and 2 control inputs, the switching unit 6 is closed at 1 and 2 control inputs, a decoder 10, a normalized duration driver 2 and a pulse distributor 3 are in the zero state due to a logical "1" signal at the installation inputs, to the installation input the ADR address of the multiplexer 4 receives a zero code, the output of the multiplexer 4 inside is electrically connected to its information input XI.

 When a logical “1” signal appears on the first control input (Fig. 2, a), the lock is removed from the decoder 10, the pulse distributor 3, and the switching unit 6 along the first control input. The signals from the first phase-shifting unit 5 (Fig. 2, g 1 and 2) pass through the first signal input of the switching unit 6 to its output (Fig. 2, 1 and 2) and then to the input of the first pulse shaper 7. Normalized number delay shaper pulses 14 is in the zero state due to the logic signal "1" at the input of the installation. From the master oscillator 1, pulses are received at the counting input of the pulse distributor 3 (Fig.2, b).

 When the n-th pulse appears at the counting input of the pulse distributor 3, the signal (Fig. 2, 4) appears on the information output n of the pulse distributor 3, which, passing through the input XI of the multiplexer 4 to its output, acts on the input of the second pulse shaper 9. The signal from the output of the second pulse shaper 9 (Fig. 2, d) translates the signal at the output of the first phase-shifting unit 5 into the opposite state (Fig. 2, g 1, 2) and puts the pulse distributor 3 in the zero state (Fig. 2, 0) , as well as acting on the counting input of the decoder 1 0, increases the result at its outputs by one (figure 2, d 1).

 The signals from the outputs of the decoder 10 are fed to the inputs of the address setting of the multiplexer 4. As a result, the next input (X2) of the multiplexer 4 is connected to the output of the multiplexer 4.

 When a pulse distributor 3 appears on the counting input (after it is zeroed at the installation input by a signal from the second pulse shaper 9), the n + 1 pulse from the master oscillator 1 (Fig. 2, 5) at the information output (n + I) of the pulse distributor 3, a signal appears that passes through input X2 to the output of multiplexer 4.

 Next, the operation of the circuit is repeated, as described above.

 When the outputs corresponding to the electrical connection inside the multiplexer 4 of its output with its input XN appear at the outputs of the decoder 10 (at the inputs of setting the address of the multiplexer 4), the matching logic 11 will work (Fig. 2f) and a signal will be output from its output to the blocking input a decoder 10 blocking it in a given state.

 Next, the second pulse shaper 9 will transfer the first phase-shifting unit 5 to the opposite state (Fig. 2, 1, 2) when each N-th pulse appears on the counting input of the pulse distributor 3 (Fig. 2, 9).

 Thus, the device allows, during the start of the inverter 8, to switch continuously from Nn + I steps from the increased frequency to the nominal conversion frequency, and the change in the conversion frequency is carried out in each half-period of the conversion frequency.

 Figure 2 presents the timing diagrams of the operation of the device in standalone mode for option N 9, n 4.

 In FIG. 2: a signal at the first control input; b output pulses generated by the master oscillator 1; in pulses at each of the 9 outputs of the distributor 3; g pulses at the output of the second pulse shaper 9; d pulses at the outputs of the decoder 10; e output signal generated at the output of the matching circuit; g 1, 2 output pulses generated by the first phase-shifting unit 5; h 1, 2 output pulses generated by the switching unit 6.

 The device in a mode with an external AC control signal of the required frequency operates as follows.

At the first control input there is a signal "0" level (Fig.3, b). The second control input receives an AC signal of the required frequency (Fig. 3, a). The third pulse shaper 12 converts the alternating current signal into direct current pulses (Fig.3c), which are fed to the input of the second phase-shifting unit 13. At the output of the second phase-shifting unit 13, two pulse sequences are formed that differ in phase by 180 ^o , which arrive at the second signal input of the switching unit 6 (Fig.3, g 1, 2).

 From one pulse train from the output of the second phase-shifting unit 13, the signal is fed to the counting input of the delay driver of the normalized number of pulses 14. After the counters input K pulses (K = 1,2,3,4) of the delay driver of the normalized number of pulses 14, its output appears the logical signal "1" (Fig.3, d), which, passing through the element NOT 15, unlocks the delay driver normalized duration 2 at the input of the installation.

 After receipt of a normalized duration 2 of delay generator 2 from the master generator 1 of M pulses (M = 1,2,3,4) to the counting input of the delay generator (3, f), a logic 1 signal appears at the output of the delay generator of normalized duration 2 (Fig. 3g), which blocks the operation of the delay driver of the normalized number of pulses 14 and the driver of the normalized duration 2 at the blocking inputs, and also enters the second control input of the switching unit 6, which allows signals to pass from the second phase-shifting unit 13 to the first 7 atel pulses 6 via the switching unit (3, s 1, 2).

 Thus, after passing K periods of the external control signal and cutting off part of the next half-cycle equal to the duration M clocks of the master oscillator 1, the inverter from the external control signal starts to work.

 Figure 3 presents the timing diagrams of the operation of the device for option K 1, M 4 and an external control signal f 75 Hz.

 In FIG. 3: a signal at the second control input; b signal at the first control input; in output pulses formed by the third FI 12; g 1, 2 - output pulses generated by the second phase-shifting node 13; d output signal generated by the shaper delay the normalized number of pulses 14; e output pulses generated by the master oscillator 1; Well, the output signal generated by the delay driver of normalized duration 2; h 1, 2 output pulses of the switching unit 6.

 A parallel inverter control device can be implemented using 561 series digital circuits.

 The pulse shaper 12, the elements NOT 15, 16 are implemented according to known schemes based on the K 561 LN2, LA7 microcircuits.

 The multiplexer is implemented on the K 561 KP2 chip.

Claims (1)

 A parallel inverter control device comprising a master oscillator, a first phase-shifting unit, a first pulse shaper whose output is connected to the inverter, a first element NOT, a delayed shaper of normalized duration, the first and second control inputs of the device, characterized in that it is equipped with a pulse distributor, the outputs of which connected to the information inputs of the multiplexer, the output of which through the second pulse shaper is connected to the input of the first phase-shifting unit, the first is set the input of the pulse distributor and the counting input of the decoder, the outputs of which are connected to the inputs of the matching circuit and the address inputs of the multiplexer, it is also equipped with a switching unit, a third pulse shaper, a second phase shifter, the output of which is connected to the counting input of the delay shaper of the normalized number of pulses, the first control input devices through the second element is NOT connected to the second input of the installation of the pulse distributor and the installation input of the decoder, the lock input of which it is single with the output of the coincidence circuit, the counting input of the pulse distributor is connected to the output of the master oscillator and to the counting input of the delay driver of normalized duration, the first control input of the device is connected to the first control input of the switching unit and the installation input of the delay driver of the normalized number of pulses, the outputs of the first and second phase-shifting units connected respectively to the first and second signal inputs of the switching unit, the output of which is connected to the first pulse shaper, a second control input connected to the output and the input of the delay lock shaper normalized durations as well as driver input delay lock normalized number of pulses and the second control input is connected via a third pulse generator to the input node of the second phase shifter.

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