SU1654826A1 - Device for checking signal sequences - Google Patents

Abstract

The invention relates to computing and can be used to control the sequence of signals in various automated control systems and automation devices. A distinctive feature of the device is that it allows to issue the signal code on which the error occurred to external circuits. This makes it possible to localize the location of the fault and shorten the time for searching for faulty elements. The aim of the invention is to extend the functionality by issuing a signal code on which an error has occurred. 1 tab. 6 Il.

Description

1 The invention relates to computing and can be used to control the sequence of signals in various automated control systems and automation devices.

The purpose of the invention is to extend the functionality by issuing a signal code on which an error occurred.

FIG. 1 shows a functional diagram of the device; FIG. 2 - the functional scheme of the first encoder; in fig. 3 is a functional diagram of pulse shapers; FIG. 4 is a functional diagram of the second encoder; FIG. 5 is a functional diagram of the switch; FIG. 6 - time diagram.

The device contains the encoder 1, group 2 of p registers, register J of the number of monitored signals, group

4 pulse shapers, encoder 5, switch 6, comparison block 7, element OR 8, comparison block 9, pulse shaper 10, delay elements 11 and 12, counter 13, riri element 14, group 15 of elements And, group 16 of inputs of monitored signals, groups of 17 inputs of controlled sequence numbers, a group of 18. inputs of the number of monitored signals, a group of 19 outputs of a controlled-sequence number and an output of a 20-device error.

The encoder 1 contains (for option n 5) a group of 21 elements AND, a group of 22 triggers, a group of 23 elements AND, a group of 24 elements AND, a group of 25 elements NOT and a group of 26 elements OR.

The number code registers of the monitored signals contain Iog2n bits each. In this case, the register with

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Number 1 records the code of the signal number of the next signal first in the sequence, in register number 2 the next second, and so on.

The number of signals in the sequence code register contains (log2n-H) bits.

The shape of the 4 pulses contains a HE element 27, a delay element 28 and an AND element 29.

The encoder 5 converts the positional code into a binary code and contains (for the eight-input version) the elements OR-NOT 30, the elements OR 31, the element NOT 32 and the element AND 33,

Switch 6 contains multiplexers 34.

Counter 13 contains (log n-M) bits.

The device works as follows.

In the initial state, the triggers 22 of the encoder 1, the registers 2, -2, 3 and the counter 13 are in the zero state (the power-on reset circuits are not shown). Before starting work, the codes of the monitored signals are entered into the registers at the inputs 17, and the signal of the next signal first in the sequence is entered in register 2 j into 2 2 next with the second signal and m = 0 At this, the signal received at input 16 with number 1 corresponds to 0 ... 000, with the number 2 - 0 ... 001, with the number 3 - 0 ... 010, etc. In register 3, the inputs 18 contain the code of the number of monitored signals, and the monitored sequence containing one signal corresponds to the code О, „„ 001, two signals - code 0 ... 010, three signals - 0 ... 011, etc. . Let the sequence of signals be 1,3,3,4,5 (). Then the registers 2 {-2 y, the corresponding codes are written (2, -0 ... 000, 22 0 ... 010, 23 - 0 ... 00 24- 0 ... 011, 2ff- 0 ... 100).

In the register V3, the code 0 ... 0101 is written. The first signal in the monitored sequence is signal 1, while the trigger 22 in the encoder 1 is set to one state, opening AND 23, since the remaining inputs of this element contain logical 1 from the element inputs | NOT 25 - NOT 25 ,, o The low level signal from the inverse output of the trigger 22 closes the remaining elements AND 23g

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And 23 p. A high level signal appears at the output of the encoder element OR 261 of the encoder I, which becomes self-blocking through the And 24, element. Self-blocking is necessary for practicing the current signals when the next signals arrive before the arrival of the clock pulses (TI, Fig. 2), while the signal (in our case, the signal with number 3) triggers 22 5 is set to one, then at 26h there is no high level signal, since AND $ 23 is closed low from zero output 22 ,. A code 000 appears at the information outputs of the encoder 5, and a high level signal appears at the control output. In this case, register 2 is connected to switch 6, since the control inputs of switch 6 contain the zero code from counter 13. In comparison block 9, the codes from encoder 5 and register 215 are compared to its high level, which NOT 14 closes elements AND 15 | and the signal Error and the signal number code are not generated.

At the same time, a clock pulse is generated at a high level from the excited output of the encoder 1, which through the element OR 8 and the delay element 12 sets the counter 13 to the next state (0 ... 001) and resets the trigger 22 through the element 21, encoder 1. The delay time of element 12 is determined by the sustained response time of the logic elements of the device. The device proceeds to processing the next signal with number 3, while the output of the element OR 26 of the encoder 1 appears high, since the element AND 23z is exposed to high levels from the zero output of the trigger 22 and the single output of the trigger 22 ,. The signal at the output OR 26 becomes self-blocking through the AND 24 element and through the NOT 25 element closes the AND 23 1 and 23 elements. In addition, the AND 23 L - 24 elements are closed low from the zero output of the trigger 22. At the information outputs of the encoder 5, code 010 arrives at the inputs of block 9 of the comparison. The other inputs of the comparison unit 9 through the switch 6 are connected to the register 2g, since the control inputs of the switch 6 contain the code 0 ... 001 from

counter 13. At the output of comparator block 9, there is a high level and a high signal from the third. output of the encoder 1 is fed to a corresponding pulse generator in; in block 4, a pulse is formed which, through the OR 8 element and the delay element 12, sets the counter 13 to the next state (0 ... 010) and flips out the trigger 223 AND 21 of the encoder 1. Then the process is repeated for the remaining sigleshoes of the monitored sequence until the moment when the counter 13 takes a state equal to the code recorded in register 3 (0 ... 0101). This happens at the moment it is processed fifth monitored signal The spins and the generated clock pulse will reset trigger 225 in encoder 1 to the zero state. All outputs of the encoder t remain in the zero state, while the encoder 5 removes the control signal by turning off the switch 6. At the same time, the comparison unit 7 operates, at the output of which a high level signal appears, on the leading edge of which a pulse is generated, which through element 11 delays reset the counter 13 and registers 2 {-2p and 3. The device is ready to control the next sequence of signals. If a violation of the sequence of signals occurs (for example, a signal 2 appears instead of the signal 3), then Block 9 compares, on whose output a low level This level goes through the NOT 14 element to the bus 20 Error and opens a group of elements And 15 (- And 15, and on the outputs 18 there is a signal code on which the error occurs. Similarly, the device works with all other disturbances of monitored signals.

The table shows the correspondences of the inputs 16 and codes recorded in registers 2, - 3 ..

Claims (1)

Claim Device five 0 Unused with the outputs of the pulse shaper group, characterized in that, in order to expand the functionality of the device by issuing a signal code on which an error occurred, a group of n registers (n is the number of monitored signals), a register, two encoders, two are entered into it comparison unit, second delay element, impulse driver, NOT element, counter, group, of i elements AND (i log2n) 5, with the first inputs of AND elements of the group connected to the outputs of the corresponding bit outputs of the counter, except o, the control inputs of the switch, with the first group of inputs of the first comparison unit, the second group of inputs of which is connected to the group of outputs of the register, the group of information inputs of which is the group of inputs of the code of the number of monitored signals of the device, the second inputs of the elements AND of the group are connected to the outputs of the element NOT, the element output is NOT a device error output, the element input is NOT connected to the equality output of the second comparison unit, the first group of information inputs of which is connected to the output group of the first encoder, the second group of information inputs - with a group of switch outputs, the information inputs of which are connected to the outputs of the group registers, the gate input of the switch connected to the output of the first encoder, the information inputs of which are connected to the outputs of the second encoder and the corresponding inputs of the group pulse drivers, information inputs of the second encoder are the inputs of the controlled sequences of the device, gate input from the second encoder connected to the output of the first delay element and to the counter input of the counter, groups of inputs of the group registers are groups of inputs of the controlled sequence numbers of the device, the equality output of the first comparison unit is connected to the input of the second delay element whose output is connected to the driver input pulses output five signal sequences containing a combo connected to the reset inputs of the counter mutator, a group of impulse and group registers and a register, outputs ow, the OR element, the first delay element whose input is connected to the output of the OR element, the inputs of which connectors AND outputs are a measure of the monitored sequence of the device. pogo connected to the reset inputs of the counter and the registers of the group and the register outputs The elements and groups are outputs of the monitored sequence number of the device. 1 2 ... n Fig 1 To Inputs 16 Figure 2 f I s J Ul f Cw & ( Ul -C00 NJ H m B1 n Sa LH I 4a QB.9 FIG. five The sequence of the signal-Pasledoba / pefos / p signals is not disturbed. FIG. AT