SU736140A1 - Symbol generator - Google Patents

Description

The invention relates to automation and computing and can be used in display devices.

A well-known symbol generator, containing a register of a character code, a memory block, 5 symbols, a poll block, a vector counter, a generator, a microcommand register, function voltage generators, a beam illumination unit, a converter, a logic unit [1]. ^ten

The closest technical solution to the invention is a symbol generator containing a clock counter, serially connected first register, first decoder and memory block, whose ¹⁵ codes are connected to inputs of the second register and second decoder, which code is connected to trigger ^ 2] The disadvantage of these generators

is the complexity.

The purpose of the invention is to simplify the character generator and increase its reliability.

2

This goal is achieved by

^: that the generator contains a switch, the third and fourth registers, the third, fourth and fifth decoders, the first input of the fifth decoder is connected to the first input of the fourth decoder, the second input to the output of the fourth register, and the code to the second input of the second decoder, the first input of the third register is connected with the third input of the second 'decoder and with the first input of the fourth register, the second input of which is connected to the outputs of the memory unit and to the second input of the third register, the output of which is connected to the second input of the fourth decoder , Vkod which is connected to the second input of the storage unit, the first input switch connected to the output of the first register, a second input to the second input of the first decoder, the third input - with the output of the clock counter, and the code - with the input of the third decoder, the output of which is connected to the third input of the memory block.

3 736140

four

FIG. 1 is a block diagram of a symbol generator; in fig. 2 - timing diagram of the character generator; in fig. 3 - examples of the organization Polygrams and symbols included 5 in each Of them; in fig. 4 shows an example of the configuration of alphabet symbols formed using the proposed symbol generator.

The character generator contains the first '

- register 1, switch 2, counter 3 cycles, the first decoder 4, the third decoder 5, block. 6 memory, the third register 7, the fourth decoder 8, the fourth 15 register 9, the fifth decoder 10, the second decoder 11, the trigger 12, the second register 13.

The character generator works as follows. .20

The character code arriving at the Character Generator Input is written to the first register 1, from the outputs of which four high-order digits of the character code receive 25 to the inputs of switch 2, and the three lower-order digits of the character code to the first decoder 4. Input to the input of switch 2. the control signal shown in FIG. 2-1, the latter allows 30 passing of the higher digits of the character code to the input of the third decoder 5 and a low level signal is formed at one of the outputs of the last. At the same time the specified control signal 35

enters the gate input of the first decoder 4 and at the corresponding output of the last signal is generated high level. Using a signal output from 'third decoder 5 and ⁴⁰ The yields and the first decoder 4 is performed from the information read. corresponding cell of the polygram selection area of memory block 6.

The information is represented by a 16-bit binary word containing the sign code of the direction of the first vector of the polygram sweep along the X-axis in b-bit, in 2 — M ^: - 4-m digits is the code of the value of the first sweep vector of the polygram along the X-axis in the 5 — m digit - the sign code of the direction of the first vector · the sweep of the polygram along the y axis,

6 — m – 8 — m digits — code of the magnitude of the first vector of the scan of the polygram along the axis in 9th – 12th digits — code of the number of the polygram, c. which includes this symbol, in the 13th - 15th digits - the code of the number of the symbol in this polygram and in the 16th digit - the modulation code of the first vector of this polygram to form this symbol. From the output of memory block 6, the information of 1-ΓΟ-8-ΓΟ bits goes to the second register 13, the information of the 9th-12th digits goes to the input of the third register 7, information 13th to the 15th digits goes to the input of the fourth register 9 and 16th digit to the input of the second decoder 11.

Writing information into these registers and the second decoder 11 is carried out by the input control signal shown in FIG. 2 - 2, arriving at the corresponding input of the symbol generator.

The signal from the output of the second decoder 11 is fed to the input of the trigger 12, setting the latter to the state corresponding to the illumination or damping of the first vector of the sweep polygram for this symbol. The information recorded in the third register 7 is fed to the input of the fourth decoder 8, which is gated by the input control signal shown in FIG. 2-3, and arriving at the corresponding input of the character generator. Next, one of the outputs of the fourth decoder 8 generates a high level signal, which is fed to the corresponding input of the scanning zone of the polygrams of the memory unit 6, thereby determining the address of the scanning of the polygrams. Information from the output of the fourth register 9 is fed to the input of the fifth decoder

10, which is gated with the same input signal as the fourth decoder 8. A high level signal from the output of the fifth decoder 10 is fed to the corresponding input of the second decoder

11. Upon receipt of the input control signal shown in FIG. 2-4, the input of the counter is 3 clocks, the corresponding states are formed at the output of the last one and are fed to the input of switch 2, and the input control signal shown in FIG. 2-5, they arrive at the input of the third decoder.

5. This decoder on its codes generates a temporal sequence of pulses that arrive at the corresponding inputs of memory block 6.

Thus, the signals from the outputs of the fourth and third decoders read out information from a specific area of the sweep area of the polygrams of memory block 6. From the output of memory block 6, the 16th bit binary words is pos5 ·; 736140 6

they blunt on the inputs of the corresponding registers and the second decoder, in the 9th - 16th bits the modulation codes are contained On the illumination of the corresponding vector. From the output of memory block 6, the information of the 1st 8th digit goes to the second register 13, the information of the 9th - 16th digit goes to the input of the second decoder 11, in which the corresponding digit is gated by the output signal of the fifth decoder 10, Therefore, to the output of the second The decoder 11 passes information from one of 9-16 output bits of memory block 6. The time sequence of the modulation codes of the polygram sweep vectors for a given symbol from the output of the second decoder 11 enters the trigger input 12, setting it to the state corresponding to the illumination or blanking of the polygram sweep vectors, thereby forming the contour of the generated symbol.

Comparative tests of a symbol generator with known ones have shown that with lower hardware costs, it is possible to form symbols of better quality and in less time.

Claims (2)

The invention relates to automation and computing and can be used in information display devices. A symbol generator is known that contains a symbol code register, a symbol memory block, a polling block, a generator vector counter, a microcommand register, function voltage generators, a beam illumination unit, a converter, a 1J logic unit. The closest technical solution to the invention is a symbol generator containing a clock counter, serially connected first register, first decoder and memory block whose outputs are connected to the inputs of the second register and second decoder whose output is connected to trigger 2. The disadvantage of these generators is complexity. The purpose of the invention is to simplify the symbol generator and increase eix reliability. The goal is achieved by the fact that the generator contains a switch, the third and fourth registers, the third, fourth and fifth decoders, the first input of the fifth decoder is connected to the first input of the fourth delifter, Eggory input to the output of the fourth register, and the output to the second input of the second the decoder, the input of the third register is connected to the third input of the second decoder and to the first input of the fourth register, the second input of which is connected to the outputs of the memory unit and to the second input of the third register, whose passage is connected to the second th input of the fourth descrambler, kktorugo code. connected to the second input of the memory unit, the first input of the switch is connected to the output of the first register, the second input to the second input of the first decoder, the third input to the output of the clock counter, and the output to the input of the third decoder whose output is connected to the third input of the memory block . Ma FIG. 1 is a block diagram of a symbol generator; in fig. 2 - time diagram of the operation of the character generator; in fig. 3 - examples of organization Polygrams and symbols, input to each Of them; in fig. 4 shows an example of the configuration of alphabet symbols formed using the proposed symbol generator. The character generator contains the first register 1, the switch 2, the counter 3 so that the first decoder. 4, third cipher 5, block 6 of memory, third register 7, fourth decoder 8, fourth register 9, fifth decoder 10, second decoder 11, trigger 12, second register 13. The symbol generator works as follows. The character code that arrives at the character generator's input is written to the first register 1, from the outputs of which the four most significant bits of the character code go to the input of switch 2, and the three low-order bits of the character code to the first decoder 4. When entering the switch 2 of the control signal shown in FIG. The latter permits the passage of the higher bits of the character code to the input of the third decoder 5 and a low level signal is fixed at one of the outputs of the last one. A signal that is tentatively indicated sends a signal to the gate input of the first decoder 4 and a high level signal is formed at the corresponding output of the last decoder. . Using a signal from the output of the third decoder 5 and from the output of the first decoder 4, information is read from the corresponding cell of the choice of polygrams of memory block 6. The information is represented by a 16-bit binary word containing a directional sign code in the discharge. the first vector of the sweep of the polygram along the X-axis, in 2-ivf 4th bits - the code of the magnitude of the first vector of the sweep of the polygram along the X-axis, in the 5th bit of 6 m-8-th bit - the code of the magnitude of the first vector of the scan of the polygram along the Y axis in the 9th-12th bit - the code of the number of the polygram, c. which includes this symbol, in the 13th and 15th bits - the code of the character's measure in this polygram and in the 16th bit of the modulation code of the first vector of this polygram to form this symbol. From the output of block 6 of memory, information of the 1st-8th bits goes to the second register 13, information of the 9th-12th bits to the input of the third register 7, information of the 13th to 15th bits - and the fourth register of the 9th and 16th bits is input to the second decoder 11. The information in these registers and the second decoder 11 is written to the input control signal shown in FIG. 2-2, arriving at the corresponding input of the character generator. The signal from the output of the second decoder 11 is fed to the input of the trigger 12, setting the latter to the state corresponding to the illumination or blanking of the first vector of the polygram for the given symbol. The information recorded in the third register 7 is fed to the input of the fourth decoder 8, which is constructed by the input control signal shown in FIG. 2-3, and fed to the corresponding input of the symbol generator. Then, a high level signal is generated from one of the outputs of the fourth decoder 8, which is fed to the corresponding input of the scanning zone of the polygrams of memory block 6, thereby determining the address of the scanning of polygrams. Information from the output of the fourth register 9 is fed to the input of the fifth decoder 10, which is gated with the same input signal as the fourth decoder 8. The high level signal from the output of the fifth decoder 1O goes to the corresponding input of the second decoder 11. When the input control signal arrives shown in FIG. 2–4, the corresponding states are formed at the output of the 3 clock counter, at the output of the latter, and are fed to the input of switch 2, and the input control signal, shown in Figs 2–5, goes to the input of the third decoder 5. This decoder at its outputs, it forms a temporal sequence of pulses that arrive at the corresponding inputs of memory block 6. In this way, signals from the outputs of the chot-, vertigo, and third decoder read information from a specific area of the scanning area of the polygrams of memory block 6. From the output of the block (3 memories of 16-bit binary ones go to the inputs of the corresponding registers and the second decoder, in the 9th – 16th bits there are modulation codes about the illumination of the corresponding vector. From the output of block 6 of the information memory The 1st through 8th bits go to the second register 13, the information from the 9th to 16th bits goes to the input of the second decipher 11, in which the corresponding bit is gated by the output signal of the fifth decipher 10, therefore, to the output of the second decoder 11 passes information from one of 9-16 output bits Memory 6: The time sequence of the modulation codes of the scan vector for a given symbol from the output of the second decipher 1 arrives at the input of the trigger 12, setting it to the state corresponding to the illumination or blanking of the vector vectors, thus forming the contour of the generated symbol. symbols with known ones have shown that at lower hardware costs, symbols of better quality can be formed in less time. Claims The symbol generator contains a clock counter, a first register connected in series, a first decoder and a memory block 140 whose outputs are connected to the inputs of the second register and the second decoder whose output is connected to a trigger, characterized in that, in order to simplify increasing its reliability, it contains a switch, the third and fourth registers, the third, fourth and fifth steps (| rators, the first input of the fifth decoder is connected to the first input of the fourth decoder, the second input - to the output of the fourth re Istra, and the output to the second input of the second 4PiaFiaTOpa, the first input of the third register is connected to the third input of the second decoder and to the first input of the fourth register, the second input of which is connected to the outputs of the memory unit and to the second input of the third register whose output is connected to the second input the fourth decoder, the output of which is connected to the second input of the memory unit, the first input of the switch is connected to the output of the first register, the second input to the second input of the first decoder, the third input to the output of the clock counter, and the output to input House third decoder which output is connected to the third input of the memory unit. Sources of information taken into account in the examination 1. USSR author's certificate number 484539, cl. G 06 K 15 / 2O, 1973 2. Technical description of the EU-7O66. Noah E13.054.OO1 TO, 1973, p. 1-27