SU1030854A1 - Device for checking multidigit memory units - Google Patents

Description

The invention relates to computing and can be used, in particular, to control multi-bit operative reference devices (103U). It is known a device for controlling multi-memory blocks, in which monitoring is performed both by addresses (in a running 1 and 0 test and by bits (in a chess control test) Cl 3 The disadvantages of this device are complexity and low reliability. Most A close technical solution to the invention is a device for monitoring multi-bit memory blocks, an address counter connected to one of the inputs of the comparison circuit, and a counting trigger C. A disadvantage of the known device is that it is used in The address rain test does not provide a complete check of the memory blocks, since the control is performed with quite specific information, and precisely, at each address the information corresponds to the forward or reverse code of the address itself, while at any address the connection between bits is not checked, in which the same information is recorded, and cross-cell communications between cells (links, each cell of any bit with cells of other bits at all addresses) are not checked, which reduces the reliability of the device. The aim of the invention is to improve the reliability of the device. The goal is achieved by the fact that the second and third pulse counters, the second trigger, the element group AND the element group OR, the group of pulse counters, the AND element are entered into the device for monitoring multi-digit memory blocks, containing the first pulse counter, the first three germs and the comparison circuit. , the element OR-NOT and the element OR, and the outputs of the first pulse counter are connected to the first inputs of the elements OR groups, the second inputs of which are connected to the outputs of the elements AND groups, the first inputs of which are connected to the outputs of the second account Ik pulses, the first and second inputs of the OR element are connected respectively to the output of the element And to one of the outputs of the second pulse counter and the input of the first trigger, the output of which is connected to the first input of the element | a And, the second input of which is connected to the inverse output of the second trigger and second the inputs of elements AND of the group, the third input of the element OR is connected to one of the outputs of the first pulse counter. And the input of the third pulse counter whose outputs are connected to the inputs of the element OR NOT, the output of which is connected to the control input of the second pulse counter, a control input of the first counter pulse. The coils are connected to the direct output of the second trigger, the inputs of the comparison circuit are connected to the outputs of the pulse counters of the group, the inputs of which are the outputs of the elements OR of the group, the direct and inverse outputs of the second trigger are respectively the control inputs, the address outputs, the read output and the write output of the device, the information outputs of which are the outputs of the third pulse counter, and the third input of the And element and the counting Inputs of the first and second pulse counters are combined and are the device access input. . The drawing shows a functional diagram of the proposed device. The device contains the first 1 and second 2 pulse counters, the first 3, the second k triggers, the third 5 pulse counter, the group of elements AND 6, the group of elements OR 7. The drawing shows the checked memory block 8. The device also contains a group of pulse counters 9, a tO comparison circuit, an OR-NOT 11 element, an AND 12 element, and an OR 13 element. In the drawing, the inversion input 1 of the device is indicated. Each counter of group 9 has (ha-1) bits (where the bit is HocTb of the drive in the memory block 8 being checked), the number of counters of group 9 is equal to t. The device works as follows. Before starting operation, counters 1, 2, 5, 9 and triggers 3 and t must be installed in ccfcTOflHMe O. At the same time, at the outputs of counter 5 (nanonformation inputs of memory block 8), zeros are set, resulting in the output of the OR-HE element 11 A signal 1 appears, allowing the operation of counter 2. From the direct output of flip-flop k, the control input of counter 1 receives a signal O, blocking its operation. The inverse output of the trigger receives the signal | 1 and 1, zadakkmtsy the Record in memory 8 block and allow incoming addresses to its inputs from counter 2 through AND 6 elements. At the output of Trigger 3, an O signal is detected that blocks the operation of the I 12 element. device is that counters 1, 2 and 5 and triggers 3 and 4 when exposed to signal 1 at the counting input switch at the end of this signal, (according to its decay), consider the operation of the device in cycles. The first cycle: write and read O across the entire array of memory block 8. The device works when signals are received. Appeal to input I. When these signals are applied, counter 2 provides for N clock cycles (where N 1 is an integer j, the enumeration of all addresses in memory block 8 of the address is received through AND 6 and OR 7 elements). Counter 1 does not affect the selection of addresses in block 8, since its outputs hold zeros. In N ticks, all zeros coming from counter 5 will be recorded. At the end of the Nth cycle, trigger 3 will switch and a 1 signal will be set at its output, allowing further operation of element 12. At this, state 1 and trigger A will be switched to the input of which is from the output of the first bit of counter 2 is sent through the element OR 13, in connection with the direct output of the trigger k, a signal is set that permits the operation of counter 1 and sets the operation mode Read in memory block 8. At the inverse output of the trigger k, the signal O of the blocking elements And 6 is set. Therefore, in the next N cycles, the address search in memory block 8 is monitored by counter I. The count information is fed to the inputs of counters 9. When the memory block 8 is working properly (when reading O by / all addresses) the state of the counters 9 does not change. . At the end of the 2N cycles, the counter 5 switches to the new state and the signal O on the output of the OR-NOT 11 element is set, blocking the operation of the counter 2. Trigger t on the signal decay. arriving at its input from the highest bit of the counter 1, switches to the state O and ert) inverse output sets the signal 1, allowing the operation of the elements 12 and 6 and setting the Record mode in memory block 8. The second cycle: the recording of all code combinations at one address and the reading of information on all bits after writing each code combination. The start of the cycle is determined by a clock (). Herewith, the address comes from counter 2, and in block 8 of memory at this address, the code combination 100 ... O is recorded, which comes from counter 5.. The Reversal signal passes through the elements AND 12 and OR 13 and the transition declines; 1 trigger trigger k to state t, therefore, from the direct trigger exit k, a signal 1 is sent to the control input of counter 1. All subsequent addresses are read. At the end (2N + 1- -Ы) (ЗМ + 1) of cycles, the counter 5 switches to the state 010 .. 0, and the trigger - to the state O by setting the Record mode in memory block 8.,, During (3 .N + 2) a clock will record a new code combination (0.10,, .0) at the same address, and at the end of this clock cycle, trigger k will again switch to state 1 and again read information from all addresses will end, and end with tact of CtN + Z). Then continues the alternation of the Record mode by the selected mode Read to all addresses. In this case, each time a new code combination is recorded from the estimator 5 in the memory block 8 and after 2 tons of such repetitions, the counter 5 will return to its initial zero state and at the output of the LINEN 11 element a signal 1 will appear, allowing the operation of counter 2. This will happen at the end (2N + 2 N +2 cycles. During the next cycle, the first address, since the counter 2. during the whole cycle does not change its state, will be recorded on all

If the signal ends, the counter 2 switches to the second state (second address), and the trigger is set to state 1. Provides the mode Read information on all addresses. At this point, the second cycle ends.

At the end of the cycle, both the address being checked and all other addresses of the memory block 8 will contain zeros. Read each time the information goes to the inputs. counters 9f, the state of which, depending on the input information, is constantly changing. Circuit 10 compares the state of the counters 9 in the last cycle of the second cycle.

With proper operation of the memory block 8, at the end of the cycle, the counters 9 are installed in the same conditions, as a result of which the comparison circuit 10 will fix the health of the memory of the memory block 8. This is due to the fact that when iterating through all the t-bit code combinations, the total number of which (equals 2, the number 1 and O in each bit is the same and is -4-.

9, they

also set to the same condition.

The second cycle is then repeated at each address. At the end of the second cycle in the last address, the trigger 3 is switched to the state O, and it blocks the operation of the element, AND 12. At this, the control of the memory block 8 ends.

Thus, the correct operation of the memory block 8 is checked with all possible code combinations for all bits, since if false information is present in any address and any bit in the last check cycle at any address, counters 9 are set to different states and the comparison circuit 10 will detect a fault.

At the same time, by recording all code combinations at each address and reading information at all addresses after writing any code combination, all possible false connections between addresses and bits are also checked.

Thus, the proposed control device as compared to the known one provides a more complete check of the memory blocks. .

The technical and economic advantage of the proposed device is a higher reliability than the known.

Claims (1)

DEVICE FOR MONITORING MULTI-DISCHARGE MEMORY BLOCKS, containing the first pulse counter, the first trigger and the comparison circuit, and moreover, in order to increase the reliability of the device, the second and third pulse counters, the second trigger, are introduced into it group of AND elements, group of OR elements, group of pulse counters, AND element, OR-HE element and element. OR, and the outputs of the first pulse counter are connected to the first inputs of the OR elements of the group, the second inputs of which are connected to the outputs of the elements AND groups, the first inputs of which are connected to the outputs of the second pulse counter, the first and second inputs of the OR element are connected. and with one of the outputs of the second pulse counter and the input of the first trigger, the output of which is connected to the first input of the And element, the second input of which is connected to the inverse output of the second trigger and the second inputs of the And elements of the group, rety input of OR 'is connected to an output of the first pulse counter and pulse input of the third counter, the output of which are connected to the inputs of OR-NO element whose output is connected to the control input of the second pulse counter, the control input of the first pulse counter is connected to a direct calculation _of stroke of the second trigger, the inputs of the comparison circuit S are connected to the outputs of the pulse counters of the group, the inputs of which, the outputs of the elements OR groups, the direct and inverse outputs of the second trigger are respectively the control inputs , Addressable outputs the read output and the output of the recording data outputs which are the outputs of the third pulse counter, and the third input of the AND and the counting input of the first and second pulse counters are combined and input device handling. SU „., 1030854 103085¼