SU1339659A1 - Apparatus for monitoring shift register - Google Patents

Abstract

The invention relates to computing and can be used to monitor shift registers operating in parallel modes, receiving information and shifting it. The aim of the invention is to increase the reliability of the control of the shift register due to the possibility of detecting a failure in the very first shift cycle after its display. For this, a second D-trigger and is inserted into the monitoring device. element and NOT. During the shift, the register is filled with the information inverse to the one that was entered in its low-order bit. The failure in the register is recorded after matching the following codes: the code entered in the low-order bit of the register, the same code after passing through the register and its inverse code after passing through the register. In case of failure, the last two codes are the same. 1 il. with "(L from 00 about :) ate with

Description

And it's more or less relevant. technology and can be used to control the reg isstry of the shift.

The purpose of the invention is to increase the reliability of control due to the possible detection of a failure in the very first shift cycle after its appearance.

The drawing is a diagram of the device

Register control device

1 shift contains the first 2 and second 3 D-triggers, the first 4 and second 5 elements are EXCLUSIVE OR, the first 6 and second 7 elements are AND, the element OR is NOT 8 and the counter 9. The drawing also shows the input 10 for setting the shift mode, input 11 settings of the recording mode, the first 12 and second 13 informational inputs of the device, the control 14 and informational 15 outputs of the device. The control shift register has parallel information inputs 16, a recording resolution input 17, a sequential information input 18 and a shift input 19, the parallel information input of the first bit and the output of the last bit of the controlled shift register 1 being connected to the first J2 and the second 12 the respective inputs of the device, respectively. The serial information input 18, the shift input L9 and the input resolution 17 of the record of the controlled shift register 1 are connected respectively to the information output 15, input 10 and input 11 of the device,

The device for controlling the shift register works as follows.

Shift register 1 operates in a parallel mode of receiving information from inputs 16 by a signal applied to input 17, with subsequent information shift using input shift signals 19,

The task of the device is to detect failures of the shift register 1, which means that in one of its bits a constant 1 or 0 is fixed,

The operation of the device is considered as an example when (where n is the number of bits of shift register 1), and code 10101 is received in shift register 1,

The essence of the control of register I is that, when zacis is in the first digit of the register of 1 unit, this unit shifts to the n-th bit of register 1 and then is rewritten into B-tr.

ger 2, and register 1 is filled with the zeros set from input 18. As a result, code 01 is written in the last bit of the register and in D-flip-flop 2, In the case of writing to the first bit of the 1 register of the zero shift, after the shift in the last bit The de 1 of the shift and the D-flip-flop 2 write the code 10, t, e, different codes.

Counter 9 should form a single signal after the occurrence of the n clock cycles of information in the I shift register. For this, the initial binary code is written to the counter 9 by a signal at the input 1I of the device so that after passing the n shift pulses, a single signal is generated at the output of the counter 9 for gating the elements 6 and 7.

When writing information to the shift register 1, the D-flip-flop 3 is set to the state corresponding to the first register bit. Since the information input 18 of the shift register 1 comes from the inverse output of the D-flip-flop 3, as information is shifted in the shift register I, it is filled with zeros (units) if the first digit is written. (Zero) After n of the first shift pulse, the unit of the first bit is copied to the D-flip-flop 2, In this case, the counter 9 generates a single signal at its output that polls AND 6 and 7 elements. When the shift register 1 is working correctly, the EXCLUSIVE OR 4 and 5 elements of the single signal are your exits after the nth so hectare shift you it is processed, and therefore no error signal is generated at the output 14 of the device.

If there is a fault in shift register 1 that results in the occurrence of a constant J or O, for example, in the third discharge of shift register 1, then after the passage of shift pulses in the nth (fifth) discharge of shift register 1 and D-flip-flop 2, codes 11 and 00 will be recorded respectively. In the first case, an EXCLUSIVE OR 4 element is triggered, to one input from which the inverse output of D-flip-flop 3 goes to zero, to another input from input 13 of the device it is a logical unit, and EXCLUSIVE OR 5, to one input which is directly connected the output of the D-flip-flop 3 is a unit, and the other input is zero from the direct output of the D-flip-flop 2. A single signal from counter 9 interrogates the elements 6 and 7, one of which produces a single signal that passes at the output 14 of the device and signals the failure of shift register 1,

Claims (1)

Invention Formula A device for controlling the shift register containing the first D-flip-flop, two AND elements, two EXCLUSIVE OR elements and a counter, the counting input and the initial setup input of which are respectively the input of the shift mode setting and the input of the recording mode of the device, and the output is connected to the first inputs elements And, characterized in that, in order to increase the reliability of the contact the roll, the second D-trigger and the OR-NOT element are entered into it, the C-inputs of the first and second D-flip-flops are connected respectively to the counting input and the input of the meter initial installation, the first inputs of the first and second elements are EXCLUSIVE OR connected to the inverse and so on The second outputs of the second D-flip-flop are with the D-input and the direct output of the first D-flip-flop, and the outputs are with the second inputs of the first and second And elements, the outputs of which are connected to the inputs of the OR-NOT element, the output of which is a control output devices a, the D inputs of the second and first D flip-flops are respectively the first and second information inputs of the device, and the inverse output of the second D flip-flop is the information output of the device. eight U Editor N.Lazarenko Compiled by A. Derugin Tehred M. Didyk Proofreader M. Pojo Order 4232/44 Circulation 589 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4