SU964646A1 - Shift register testing device - Google Patents

Description

001 ... 100. After one set of synchronization, the register has a state at the end of the cycle 01 ... 1000, i.e. this information in relation to the incoming one will be distorted, and the control circuit for the first and last trigger of the register will not detect this distortion. The purpose of the invention is to increase the efficiency of controlling the shift register by fixing faults caused by the disappearance of one or several synchronization pulses. The goal is achieved by the fact that the device for controlling the shift register containing the parity block, the first and second modulo-two adders, the first trigger, the first element 2IILI, the first and second elements AND, and the information inputs of the controlled register are connected to the inputs parity control unit, the output of which is connected to the first input of the first modulo two, the output of which is connected to the first input of the second modulo two, the input of the device is connected to the first inputs of the first and second elec And, with the clock input of the controlled register, with the first input of the first element 2И-OR, the output of which is the output of the device, the OUTPUT of the first trigger is connected to the second input of the first adder two, the direct and inverse inputs of the received information of the device are connected respectively the third and fourth inputs of the first and second elements are And, the outputs of which are connected respectively to the single and zero inputs of the first bit of the Controlled Register, introduced the third and fourth modulators of two second and third triggers , the initial setting shaper, the waiting multivibrator, the first and second elements are NOT, the second, the third and fourth elements are 2I-OR, and the input of the initial installation of the device is connected to the input of the waiting multivibrzor, with the synchronous input of the second trigger of the initial installation and with the input of the first element NOT, the single output of the second trigger is connected to the second input of the initial setup shaper, the first input of the second element 2И-OR, the output of which is connected to the synchronous input of the first trigger, the output of the first elements connected to the second input of the second element 2I-OR, the zero output of the second trigger is connected to the third input of the second element 2I-OR and to the first input of the third modulo two; the output of which is connected to the second input of the second adder modulo two, the output of the third trigger is connected to the second input of the third adder modulo two and to the first input of the fourth adder modulo two, the outputs of the second and fourth modulators two are connected respectively to the second and third inputs of the first element 2I-OR, the output of the waiting multivibrator is connected to the fourth input of the first-element element 2I-OR, the unit of the second trigger is connected to the second input of the fourth modulo two, the output of the second element AND dinene with the fourth input of the second element I, the first output of the initial setup shaper is connected to the installation input of the first digit of the first register to zero, with the installation input of all other bits into the unit, with the first single input of the third trigger and with the first input of the third element 2I-OR , the output of which is connected to the zero input of the first trigger, the second output of the initial setting generator is connected to the first zero input of the third trigger, to the installation input b of the first digit of the controlled register and with the first input of the fourth element 2И-OR, the output of which is connected to the single input of the first trigger, the control input of the device is connected to the second inputs of the third and fourth elements 2И-OR and through the second element NOT with the third inputs of the third and fourth elements 2И-OR, the output of the first element is NOT connected to the fourth input of the fourth element 2И-OR, the fourth input of the third element 2И-OR is connected to the input of the logical unit, the third and second control you ode controlled registers are connected respectively to the second unit and the zero input of the third flip-flop. The initial setup driver contains the first and second NAND elements, the first input of the imaging unit connected to the first inputs of the first and second IAN elements, the outputs of which are respectively the first and second outputs of the imaging unit, the second input of the imaging unit "O"

one with the second input of the first NAND element, the output of which is connected to the second input of the second NAND element.

Figure 1 shows a block diagram of a device for monitoring the shift register; FIG. 2 is a block diagram of an initial setting generator,

As a controlled shift register (FIG. 1), the potential-impulse register 1 is represented. On static triggers 2.1-2, the direct and inverse information inputs of the device are connected via the first 3-0 and second 3.1 elements, respectively, to the single and zero inputs of the controlled register 1, the register includes elements of AND 3.2-3 (n + 1), in addition, the device includes the first central control unit, the second 4.1, the third, 3 and the fourth .2 elements 2И-OR, the first 5-1 , second 5.2, third 5.3 and fourth B, adders modulo d% a, block 6 of parity control, first t The rigger 7, the first 8.1 and the second 8.2 elements are NOT, the second 9 and the third 10 are triggers, the initial setting generator 11 and the waiting multivibrator 12, the first 13 and second generator of the initial installation 11, the second one. 1 are non-NOT elements whose outputs are shaper outputs.

The initial setting (NC) of the shift register and control elements triggers is performed before each word shifted prior to the start of the clock pulse set, equal in number to the number of static triggers in the register. The control device can be conventionally divided into an information control circuit that monitors the shifted information at each shift cycle and a synchronization fault monitoring circuit, which monitors the synchronization failure after each shifted word.

The GO of the CS output locks on the fourth input the first two-input element 2И-OR., Intended for the output of the error signal in case of synchronization failure, and the duration of the inhibit is chosen equal to the duration of the passage of the burst (in this case, three). The impulse of the initial setup, hit the counting input of the second trigger 9, sets

0 it in one of the states (O or 1), changeable with each word of information. For example, suppose it. will be set to state 1. According to this, as well as by impulse (at the control input), the driver P of the initial setting (FIG. 2) generates a zero potential at the output of the first IS-HE 13, and at the output of the Bfpporo element AND-NOT 1 0 unit potential. A high potential from the first output of the imaging unit 11 is fed to the input of the installation in the first discharge register register and to the installation input to all others. The zero potential from the second output of the former 11 sets the trigger per jBoro bit register in the unit as well. all other bits in NOLB. In addition, the third trigger 10 is also set to the zero state. After the termination of the signal at the control input of the device, the outputs of the driver 11 will have unit potentials that do not change the state of the register and the third trigger. Thus, the zero signal from the output of the trigger 10 and the signal 1 from the direct output of the second trigger 9 are set to output 46 4. The control of the shift register will be considered on a specific example of a register consisting of three static triggers. In this case, a logical unit is fed to the control input. With the arrival of a pulse in the initial setup, following in front of each wad of clock pulses with a constant time. multivibrator 12 from its inverse fourth adder 5 error signal, which will pass to the output of the first two-input element 2И-OR at the end of a pack of three pulses in case of at least one synchronization pulse disappear, as a result. what is the control unit, the first bit of register 1, is not entered in the trigger 10 and eliminates the error at the output of the adder 5, In the trigger .7 pax 2 registers, except for the first one, the information on the erroneous information (in this case, zeros), and only exact number of packs. pulse will lead to rewriting into the control trigger 10 error-free control information recorded in the first digit of register 1, and, consequently, to the absence of an error at the end of the word on synchronization sbs,. A similar control on the synchronization failure occurs with the arrival of a new control signal (i.e., with a new information word), but with a record, in accordance with the changed state of trigger 9 from H to O, for the first time of trigger 2 - zero , and in the remaining triggers 2 registers and the third trigger 10 units. The monitoring of the shift register operation with each tick of the incoming parity information occurs as follows. According to the example, when the output of the second flip-flop 9 is one, and accordingly, in the first discharge of register 1 also 1, in the first - flip-flop 7, in flip-flops 2.2, 2.3 and in the third flip-flop 10-zeros, In this case, at the input of block 6 there is information 100, and the result at its output is a unit that arrives at the first input of the adder 5.1) at the second input of which is a unit from the output of the first trigger 7- Error signal. Before the arrival of information at the input of the register adder 5-1 is absent. Suppose a single information arrives at the register input with the first clock cycle, then the information at the input of block 6 will change to 110, therefore, from the output of block 6, the first input of the first adder 5.1 will receive a zero signal, which should lead to an error at the output of adder 5.1 but, due to the fact that the unit arriving along with the register input clock coincides with the direct output unit of the second trigger 9, the first input of the two-input element 2И-OR will be k .. This unit will go to the counting input of the first trigger 7, installing it

remove the amount of error condition

torus 5.1 and not allowing it to pass through the first input of the prohibition element., which indicates that the given unit of information is correctly recorded in the register.

from the output of the block

remaining units - units, 6 will be unit.

Claims (2)

The proposed device allows detecting any errors in the register 6. Suppose that the input together with the second clock is zero information, then at the input of block 6 it will be after shifting Oti, therefore, the output of block 6 will not change (O), at the same time the signal from the zero input from the element 3, with the presence of the second bar, through. the fourth input of the second two-input element 2I-OR - k. will pass, since it is closed by the zero potential of the trigger 9, therefore the unit information will not arrive at the counting input of the trigger 7 and it will remain in the zero position, i.e. an error at the output of the adder 5-1 is missing, which indicates the correct recording of information (in this case, zero). Let the third tick receive a single information, then at the input of block 6 it will be after the shift 101, the control unit will be written into trigger 10, at the output of block 6 it will be O, and on triggering trigger 7 - 1, since the received unit of information will change its state “And from the output of the adder 5.1, the unit will go to the first input of the adder 52, at the second input of which is also a unit, and, consequently; there is no error signal at the device output. Similarly, the performance of the parity shift register is monitored when the next LC pulse arrives, only in this case, in connection with setting the trigger 9 to the zero state, the information in trigger 7, in trigger 10 and in register triggers is written inverse and check digit d, about moving through the register, is not M, but TT. The performance of the shift register with an even number of flip-flops 2 is different in that the control input (the logical input is given a logical zero and each trigger NU trigger 7 is set only in one state to avoid an error on the adder 5.1, as when writing one in the first trigger 2, and the rest - null, as well (with a new impulse NU) when writing zero in the first trigger 2 registers, and in re shift with an unlimited number of bits, both with an even number and an odd number. d the shift register control containing the parity check block, the first and second modulo-two adders, the first trigger, the first element 2И-OR | the first and second AND elements, and the information outputs of the controlled register are connected to the inputs of the parity check block whose output is connected with the first input of the first modulo two, the output of which is connected to the first input of the second modulo two, the clock input of the device is connected to the first inputs of the first and second And elements, to the clock input of the controlled re gistra, with the first input of the first element 2I-OR; the output of which is the output of the device, the output of the first trigger is connected to the second input of the first modulo-two adder, the direct and inverse inputs |; 1 of the received information of the device are connected respectively to the second inputs of the first and second And elements, the outputs of which are connected respectively to one and zero the inputs of the first bit of the controlled register, characterized in that, in order to increase the efficiency of the control unit, the third and fourth modulo-two adders, the second and the third triggers are entered into the device first installation, waiting multivibrator, first and second elements NOT, second, third and fourth elements 2И-OR, and the input of the initial installation of the device is connected to the input of the waiting multivibrator, with the synchronous input of the second trigger, with the first input of the generator of the initial installation and with the input of the first of the NOT element, the single output of the second trigenera is connected to the second input of the initial setup generator, to the first input of the second element 2И-OR, the output of which is connected to the synchronous input of the first trigger, the output of the first element AND Connected to the second input of the second element 2I-YLI, the zero output of the second trigger is connected to the third input of the second element 2I-OR and to the first input of the third summator modulo two, the output of which is connected to the second input of the second modulo two adder, the output of the third trigger is connected to the second input of the third adder modulo two and with the first input of the fourth modulo two, the outputs of the second and fourth modulators two are connected respectively to the second and third inputs of the first element 2И-OR, the output of the waiting cartoon A vibrator connected to the fourth inlet. home riepBoro, element 2И-OR, the unit output of the second trigger is connected to the second input of the fourth modulo-two adder, the output of the second element I is connected to the fourth input of the second element I, the first output of the initial setting generator is connected to the input of the installation to zero first digit controlled register with the installation of all other bits in the unit, with the first single input of the third trigger and with the first input of the third element 2И-OR, the output of which is connected to the zero input of the first trigger, the second output of the ovatel initial installation connected to the first input of the third flip-flop zero, by setting the input unit in the first discharge register and controlled. with the installation input of all other bits to zero and with the first input of the fourth element 2И-OR, the output of which is connected to the single input of the first trigger, the control input of the device is connected to the second inputs of the third and fourth elements 2И-OR and through the second element NOT to the third the inputs of the third and fourth elements 2I-OR, the output of the first element is NOT connected to the fourth input of the fourth element 2I-OR, the fourth input of the third element 2I-OR is connected to the input of the logical unit, the third and second control outputs ontroliruemogo register are respectively connected with a second single-mi and zero-input of the third flip-flop. 2. The device according to claim 1, characterized in that the initial setup driver comprises the first and second AND-NES elements, the first input of the imaging device being connected to the first inputs of the first and second 11 96i “64612 NAND elements whose outputs in-Sources of information first and second, respectively, taken into account in the examination Eye out shaping, Tuesday1. USSR author's certificate the input of the former is connected to the second Iff 399862, cl. G, OE F, 197. the entrance of the first element AND-NOT, vy.khod5 2, USSR author's certificate which is connected to the second inletN, cl. G 06 F 11/08, 1378 the second element is NOT. .(prototype). Phage.g