SU1550502A1 - Generator of recurrent sequence with self-check - Google Patents

Abstract

The invention relates to digital computing and can be used to generate evenly distributed input sequences for stochastic control of digital devices and to simulate random processes in ensuring the reliability of discrete systems. The purpose of the invention is to increase the reliability of the device. The generator contains N - bit Huffman filter 1, delay element 2, decoder 3, counting trigger 4, control unit 5, memory trigger 6. Control unit 5 is designed to determine the failures of the recurrent sequence generated by the proposed generator and the "parity check" malfunctions. The goal is achieved by introducing a delay element 2, control unit 5. 1 hp f-ly, 6 ill.

Description

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FIG. one

j The invention relates to digital computing and can be used to generate evenly distributed input sequences for stochastic control of digital devices and to simulate random processes in ensuring the reliability of discrete systems.

The purpose of the invention is to increase the reliability of the generator0

Figure 1 presents the structural scheme of the proposed generator of a recurrent sequence with self-control; Fig. 2 is a block diagram of an n-bit Huffman filter; fi g 3 - block 7 schema of the decoder; on fkg.4 - block diagram of the control unit; NOT: FIG. 05 is a timing diagram of the operation of a self-checking recurrent sequence generator; figure 6 - the same

The proposed self-checking recurrent sequence generator contains an n-bit filter 1 Xa fnen, delay element 2, decoder 3, counting trigger 4, conrol unit 5, memory storing trigger 6

Huffman n-bit filter 1

(FIG. 2) contains element 1 2ILI, shift register 8, adder 9 for fashion

lx

two.

As an n-bit Huffman filter 1, a known device is used based on a recurrent sequence generator.

The decoder 3 contains the elements 10 and P, the element NOT 12, the element | nt AND-NOT 13, the element 2 and 14, the element OR-NOT 15.

The control unit 5 contains the item W) AND-NOT 16, the item NOT 17, the counter 18

Decoder 3 is used to automatically write the unit to the Huffman p-ractable filter 1, to organize the passage of signals inside the device.

Counting trigger 4 is designed to count the number of zeros in the sequence after 0

The control unit 5 is designed to determine the failures of the recurrent sequence period generated by the proposed generator and the parity check failures.

Trigger 6 Memorization is intended to register a fault.

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or a recurrent sequence generator.

The self-checking recurrent sequence generator works as follows0

When the power is turned on, the state of the triggers, the counter, may be arbitrary

The RESET signal is a pulse with a low active level, which is determined by the time of setting the logic level 1, at the synchronization input of the trigger 6 of memory. By the RESET signal that goes to the second input of the n-bit Huffman filter 1, the third input of the counting trigger 4, the fourth input of the memory trigger 6, will set the zero outputs of the shift register 8 of the C-bit Huffman filter 1, the first output of the counting trigger 4, the memory trigger 6 will be set to 1. Logic levels O from all outputs except the first, n-bit Huffman filter 1 are supplied to (p-1) inputs of element 10 (p-1) OR-NO, respectively, the logical level 1 is set at its output, which is inverted by element 12 and arrives in the form of a logic level O to the second input of element 2I 14, thus prohibiting the passage of pulses from the output of element 2 of the delay through this element. The logic level O from the output of the element NOT 12 is also fed to the first input of element 2 OR-NOT 15 and together with the logic level O supplied from the first output of the n-bit filter

1Huffman to the second input element

2OR-NOT 15, sets the output of this element to a logic level 1, which is fed to the first input of element 2 OR 7 p-bit Huffman filter 1 and sets the output of this element to the logical 1, which is supplied

to the input of the sequential entry of D when you shift to the right of the register 8 shift. The level of logic 1 from the output of element 10 (p-1) OR-NOT also goes to the second input of element 2 OR- NOT 1 I and sets the output level of this element to the level of logic O, which goes to the second input of element 2I-NOT 13 thus prohibiting the passage of pulses from the output of delay element 2 through this element The level of logical 1 from the output of element 10 (p-1) OR NOT is also fed to the input of element NOT 17 of control unit 5, setting the level of logical O at the output of this element to the control input V of the n-bit counter 18, At the control input V of the n-bit counter 18 of the logical level O, a code of a sequence length of 2P-2 is written into this counter 0 After writing the code, the binary sequences in the n-bit counter 18 at the output of the reverse transfer P of this counter are set the logic level 1, which is fed to the second input of the element 2IL-NOT 16 and sets at its output the logic level O, which is fed to the third input of the memory trigger 6. The level of logical 1 from the output of element 10 (p-1) OR-NOT is also fed to the second input of the trigger 6.

The process of generating a recurrent sequence at the output of the proposed device occurs simultaneously with the control of this sequence and is carried out as follows. At the input of the CLOCK FREQUENCY, pulses with a high active level appear, which arrive at the first input of the n-bit Huffman filter 1 and the input of the delay element 2,

Upon the arrival of the first pulse at the input, the CLOCK FREQUENCY logic level 1 from the input of the sequential P + input when the shift register 8 is shifted to the right, the Huffman –n-bit filter 1 is written to the first digit of this register, which is the first output of the Huffman G n-bit filter . The level of logic 1 from the first output of Huffman’s 1-bit random filter 1 goes to the second input of element 2 OR-NOT 15 decoder 3 and sets the output of this element to the logic level O, which goes to the first input of element 2 OR 7 N-bit Huffman filter 1, allowing thereby the passage of the signals from the output of the adder 9 modulo two through this element.

At the arrival of the second pulse at the input, the CLOCK frequency is logical

Level 1 appears at the second output of the 8-shift register, which is the second output of the n-bit Huffman filter 1 and goes to the first input

 element 10 (n-l) OR NOT, set at the output of this element the level of logical O, which is fed to the input element NOT 17 of block 5

Q control and sets at the output of this element the logical level 1, thereby prohibiting the entry of the code of the sequence length in the n-bit counter 18. Thus, the n-section counter 18 is ready to count the pulses arriving at its input in the mode subtraction -1. The logical level O from the output of element 10 (p-1) OR is NOT fed to the input of the element NOT 12 and sets the output of this element to the level of logical 1, which is fed to the second input of element 2И 14, thereby allowing the passage of pulses from the output of the element

5 2 delays through this element0 Thus, the pulses from the input CLOCK FREQUENCY, the passage through the element 2 delays and the element 2 and 14, arrive at the counting input in the subtraction mode -1

0 n-bit counter 18 block 5 control ,,

By the difference of each pulse at the input of the CLOCK FREQUENCY from the state of logical O to the state of logical 1, information is shifted in shift register 8, as a result of which a recurrent sequence of levels is generated at the output of the n-bit Huffman filter 1

0 logical 1 and O The logical level O from the output of element 10 (p-1) OR NOT-decoder 3 is fed to the second input of element 2 OR-NOT I1, thereby allowing the passage of the signal

5 float from the n-th output of the Huffman p-bit filter 1 through element 2OR-NOT 11. In the case when the n-th output of the n-bit filter 1 of Huffman 1, which is also the first

0 input element 2ILI NOT 11 decoder 3, set the logical level O, the last passage through element 2 OR-NOT 11, is inverted and fed to the second input of element 2I5 NOT 13 as logical level 1, thereby allowing the passage of pulses from the output of element 2 delay through this item. Thus, the pulses from the input CLOCK FREQUENCY

pass through the delay element 2 and, through the element 2I-HE 13, inverted and fed to the second input of the counting trigger 4 in the form of pulses with a low active level. When installed on the n-th output of the n-spread Huffman filter 1 level logical 1, the last pass through the element 2Sh1I-HE 11, inverts the SL and goes to the second input elec- the form of the logical level, thereby prohibiting the passage of pulses from the output of element 2

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drops to the third input of the trigger 6 memory. According to the Lepadade of the second pulse, which is also the first pulse of the next cycle of the recurrent sequence, at the input of the CLOCK FREQUENCY from the state of logical O to the state of logical 1 on all outputs except the first, n-bit filter 1 of Huffman, the levels of logical O are set. what happens when the maximum length of one cycle of a recurrent sequence. Logical O Levels

ten

20

delay through this item on the second. from all pins except the first one, the input of the counting trigger 40 Thus, the second input of the counting trigger 4j is pulsed only when the output of the n-bit of the Huffman filter 1 is set to the logic level. The counting trigger 4 counts these pulses, which is equivalent to counting the number of zeros in a recurrent sequence, In the case of an even number of zeros in one center, after the code of the recurrent sequence at the output of the counting trigger, to

Huffman's n-bit filter 1 is given to the corresponding inputs of ment 10 (p-1) OR NOT-decrypt and the logic level is set to 1 at the output of this ment, the passage through element 2 OR-NOT 11, invert, enters respectively on ele 2and 14 and 2I – HE 13 in the form of a level 25 O, thereby prohibiting the passage of pulses from the output to the elec- tor 2 delays through these elements, blunt to the second input of the trigger of the minani. Since on the third input of trigger 6, memory set the logic level 1, then the state of this trigger will not change, which indicates the health of the generator of the succession sequence. The logical 1 is also placed at the input of the HE element 17 of the 5 l block and sets the logical logic O at its output, which is fed to the control input of the V-th counter 18. When the logic level O is received, the control V is n-bit counter 18 of this counter, the sequence length code is reset, causes the output of the transfer wiring pattern P ... to logical state 1. Upon the arrival of the () th impulse which is also the second and the next cycle of the recurrent sequence at the input of SO FREQUENCY logic level 1 is in the second bit d reg page shear and process self control torus recurrent follower

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4 sets the logic level O, which corresponds to the symptom of the absence of a malfunction in parity control, and in the case of an odd number of zeros in one cycle of the recurrent sequence code, the logic level is 1, which corresponds to the symptom of the malfunction and | cedovatnosti in the control of the couple) STI.

By the difference of the (2 -2) th pulse coming from the output of element 2I 14 n | and the counting input in the subtraction mode –I n-bit counting 18 of control unit 5, from the logical state to the logical O state, The installation at the output of the inverse transfer P of the p-bit from the rutcher 18 of the block 5 of the logic level O control, which is fed to the second input of the element 2IL-NOT 16. At the same time, in the case of an even number "hive in the loop of the recurrent sequence code at the output of

An n-bit filter is given for the corresponding 10 (p-1) OR and set the level of the log on the ment, the passage through the element 2 OR-NOT 1 enters the corresponding 2I 14 and 2I-NOT 13 into 25 Oh, the prohibition of the impulses 2 Delay through e stumbles on the second in minani. Since the trigger 6 of the memory, the logic level of this trigger does not indicate the correctness of the successive logical 1 sequence to the input of the element Nl and sets the logic level to the control counter 18. The level of the logic input V n-bit of this counter of the code of the length of the sequence results in the establishment of the transfer P .. in the composition 1. On arrival (2, which is also the next qi of the sequence of the FREQUENCY sequence, the logical in the second shift p and the torus process is recurrent

rigger 4 sets the level of logical O, which goes to the first input of element 2ШШ-НЕ 16, starts anew, lock 5 is checked. Thus, if these conditions are met, the level of logical 1 is set at the output of element 2 OR 16; decomposition of max n-bit filter

0

 from all conclusions except the first,

which is NOT 12 and

0

The n-bit Huffman filter 1 is fed to the corresponding inputs of element 10 (p-1) OR-NOT decoder 3 and the output of this element is set to logical 1 ry, the passage through element 2 of OR-NOT 11 is inverted and fed to elements 2 and 14 and 2 and NOT 13 in the form of a logical 5 O level, thereby prohibiting the passage of pulses from the output of the delay element 2 through these elements, and is fed to the second input of the trigger 6 memory. Since the third input of the trigger 6 of memorization is set to logic level 1, the state of this trigger does not change, which indicates that the generator of the recurrent sequence is healthy. The logic level 1 also enters the input of the NOT element 17 of the control unit 5 and sets at its output the logic level O, which goes to the control input V of the p-bit counter 18. When the logic level O arrives, the control input V is n-bit counter 18, the sequence length code is overwritten in this counter, which sets the reverse transfer output P ... to the logical state 1. Upon the arrival of the () th pulse, which is also the second pulse of the next cycle of the recurrent sequence at the input the CLOCK FREQUENCY logic level 1 is recorded in the second bit of the shift register 8 and the process of self-control of the recurrent sequence generator

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50

starts again, starts again,

In the event of failures (Fig. 6), leading to the decomposition of a cyclic -sequence of the maximum length of the Huffman n-bit filter 1 into

the segments whose lengths, no i, are the difference of the (2h-jl) th pulse, where J 1 coming from the output of element 2I 14 to the counting input in the subtraction mode is 1 n-bit counter 18 of the control unit 5, from logical 1 ABOUT,

inverse output

the logical state, the previously set logical level 1

the transfer of the P n-bit counter 18 of the control unit 5 does not change, since the installation of the logic level O at this output occurs only by the (2m-2) -th pulse from the output of element 2I 14 to the counting input in subtraction mode -1 n-bit counter 18 of control unit 5, from the state of logical 1 to the state of logical logical 1

transferring the P n-bit counter 18 of the control unit 5 to the second input of element 2 OR-NOT 16 and setting the output of this element to the level of logical O, which is fed to the third input of trigger 6 of memory. By the difference (2n-, j) -ro pulse, which is the first pulse of the next cycle of the recurrent sequence, at the input the CLOCK FREQUENCY from state 0 to logical, on all but the first outputs,

a sequence that corresponds to the symptom of a failure or collection of a generator of a recurrent sequence at parity control at the output of trigger 4 sets a logical level I, which is fed to the first input of the element 2IL-NOT and sets the output level of the element It enters the third input of the trigger 6 memorization. Further events leading to the installation at the output of the trigger 6 of memorizing a level logical 15 O are described in the previous case. Thus, the self-checking scheme of the proposed generator, besides the even one, also detects an even number of errors in the recurrent successor.

ten

O. Level from the inverse output

2Qs, as well as failures, leading to the cyclic succession of the maximal length of the n-bit 1 Huffman filter 1 into segments whose length m is 2n-1,

25

Claims (2)

Invention Formula chesky hi ti 1, A self-monitoring recurrent sequence generator, containing a 30 Huffman p-bit filter, a decoder, a counting trigger, a memory trigger, with the clock input of the n-bit Huffman filter connected to the clock input of the Huffman's n-bit filter 1 is set to 35 t ° Pa, the reset input of which connects the levels of logical O, To the reset inputs of the counting trigger and the memory trigger, the output of which is connected to the output of the Norm / Not good condition of the generator, the information output of which is connected to the nth output of the n-bit Huffman filter, characterized in that it has a delay element and a control unit, and the generator reset input is connected to the reset input n times the Huffman filter, whose information input is connected to the first output of the decoder, the first input of which is connected to the clock input through the delay element The n-bit generator of the n-bit filter is connected to the inputs from the 2nd p n + 1 decoder, the second output of which is connected to the read input of the control unit, the output of which is connected to the data input of the trigger of storing the synchronization input and control The control input of the control unit is connected to the corresponding inputs of the element 10 (nl) OR NOT of the decoder 3 and set at the output of this element the level of logic 1, which, passing through the element NOT 12 and the element 2 OR-NOT 11, is inverted and fed respectively to the elements 2 and 14 and 2 and NOT 13 in the form of a logic level O, thereby prohibiting the passage of pulses from the output of the delay element 2 through these elements, and is fed to the second input of the trigger 6 memory. According to this difference, at the second input of trigger 6, the output of this trigger is set to a logical state O, since the third input of this trigger is set to a logical level O what happens if there are faults in the generator of the recurrent sequence or failures in the latter. In the case of an odd number of zeros in one cycle of the recurrent code sequence, which corresponds to the symptom of a malfunction or failure of the recurrent sequence generator during parity control at the output of the trigger 4 sets the level of logical I, which is fed to the first input of element 2 OR-16 and sets the output of this element to the level of logical-O, which goes to the third input trigger 6 memorization. Further events leading to the installation at the output of the trigger 6 of memorizing the logic level O are described in the previous case. Thus, the self-control scheme of the proposed generator, besides the odd one, also detects an even number of errors in the recurrent sequence. as well as failures leading to the decomposition of a cyclic sequence of the maximum length of a n-bit Huffman filter 1 into segments whose length m is 2n-1, 25 Invention Formula 1, A self-monitoring recurrent sequence generator containing a Huffman p-bit filter, a decoder, a counting trigger, a memory trigger, with the clock input of the n-bit Huffman filter connected to the clock input of the t ° Ra the reset input of which is connected To the reset inputs of the counting trigger and the memory trigger, the output of which is connected to the output of the Norm / Fault of the generator, the information output of which is connected to the nth output of the n-bit Huffman filter, characterized by the fact that delay and control unit, and the reset input of the generator is connected to the reset input of the n-bit Huffman filter, the information input of which is connected to the first output of the decoder, the first input of which through the delay element is connected to the clock one One generator, p-outputs of the n-bit Haffmen filter are connected to inputs 2 through n + 1 of the decoder, the second output of which is connected to the subtracting input of the control unit, the output of which is connected to the data input of the memory trigger, the control input of the control unit is connected to the third output of the decoder, the fourth output of which is connected to the counting input of the counting trigger, the installation input of which is connected to the level of the logical unit, the output of the counting trigger is connected to the input sign of the control unit First and second data inputs of which are connected respectively to the n th logical levels 1 and logical O installation storing trigger input connected to logic level | 2. The generator according to claim 1, characterized in that the control unit contains an n-bit counter, element 2 OR NOT, element NOT, and 2 L. | jigsaw The first information input of the block is connected to the combined inputs of the summation and the inputs of the parallel write bits from the 1st to the n-1 n-bit counter, the reset input of which and the input of the n-th parallel record are connected to the second information unit input, the control input of which through the element is NOT connected to the control input of the n-bit counter, the transfer output of which is connected to the first input of element 2 OR NOT, the second input of which is connected to the input of the sign of a block failure, the input of which is read from which is connected to deducting input ode n-bit counter, the output element 2 OR is NOT connected to the output of the block Reset Taktobo frequency 1script registers 2nd exit register n Exit No. w breathing 15 Out 2 Out 13 Out lit Exit Out 18 V5 output, „Norma„ fault FIG. five Reset Taxmofa frequency 1st & Exit $ Јy8 logout p 6th registrar Output Out 15 V.1 Out 13 Outlet Out 10 Outlet Outlet 18 Out five Output. „Mink is a fault 6