SU1293739A1 - Checking device - Google Patents

Abstract

The invention relates to automation and computing and can be used in hierarchical multichannel control systems as a control device and control of multichannel objects. The purpose of the invention is to expand the functionality of the device and increase the reliability of the control. The device contains an input-output unit 1, a feature storage unit 2, a first pulse shaper 3, a mode setting unit 4, a second pulse shaper 5, a synchronization block 6, an installation block 7, an I / O register block 8, a first register 9, a second ; (LC N9; about her 00; o

Description

swarm register 10, multiplexer 11, decoder 12, feature generation unit 13, pulse generator 14. The purpose of the invention is achieved by the introduction of a descrambler, a synchronization unit, an installation unit, and a driver for them.

The invention relates to automation and computing and can be used in hierarchical multichannel control systems as a control device and control of multichannel objects.

The purpose of the invention is to expand the functionality of the device and increase the reliability of the control.

FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of a feature storage unit; FIG. 3 is a block diagram of the formation of features; FIG. 4 is a diagram of the first pulse former; in fig. 5 is a block diagram of the mode setting; in fig. 6 is a diagram of a second pulse former; in fig. 7 is a block diagram diagram.

The device (Fig. 1) contains an I / O unit 1, a storage unit 2. The signs, the first pulse shaper 3, the mode setting unit 4, the second pulse shaper 5 (the driver and: -1 pulse sequence), synchronization block 6, the block 7, an I / O register block 8, a first register 9 (channel register), a second register 10 (status register), a multiplexer 11, a decoder 12, a characteristic generation unit 13, a pulse generator 14. The diagram also denotes device control inputs 15, device address outputs 16, device information outputs 17, device control output 18, device control outputs 19, device block outputs 20-62, device information inputs-outputs 63, information input 64 devices.

The block of storage of features (Fig. 2) Contains the register 65 and the decoder 66. The inputs of the register are 67, 67, Y-, the outputs of the register are 68. 68.

pulses and pulse generator. The introduction of new elements and connections also makes it possible to increase the reliability of control by checking the device by a higher level control processor. 7 ill., 2 tab.

five

fO

15

20

25

thirty

35

40

The feature generating unit (FIG. 3) contains the first element AND 69 and the second elements AND 70 70g.

The first pulse generator (Fig. 4) contains the switches 71j and the decoder 72.

The mode setting block (Fig. 5) contains a decoder 73, the first 74, the second 75, and the third 76 OR elements, the delay element 77.

The second pulse shaper (Fig. 6) contains a pulse counter 78, the first 79, the second 79, the third 79 triggers, the first 80, the second 81, the third 82 and the fourth 83 switches, the first 84, the second 85, the third 86, the fourth 87 and fifth .88 elements And, the first 89 and second 90 elements OR, the first 91 and second 92 one-shot ones.

The synchronization unit (Fig. 7) contains the first 93, second 94, third 95 and fourth 96 triggers, first 97 and second 98 elements OR, first 99, second 100, third 101 and fourth 102 elements I.

In the hierarchical control system, it is conditionally possible to distinguish three levels {S, S, Sj, the highest level S being implemented on a processor (microprocessor), level S being represented by a variety of control control devices similar to the proposed object, and finally, level S corresponds to a multitude of control objects.

The functional load between the levels of the described system is distributed as follows.

The microprocessor of the upper control level S, in multiplexing mode, carries out control devices and controls located at level B, producing control and test effects on devices

Sj level. In addition, the microprocessor of the S level also receives in the multiplexing mode information from the S level devices on the state (reaction signals), 5n SA level control objects and their own state of the S level devices in their test mode.

ts

and processes it.

The operation of the decoder 66 of the feature storage unit 2 is characterized by the table. of truth.

The operation algorithm of the decoder 73 is defined in the following table. 2

The device works as follows.

Consider the principle of operation of a device that operates in the following modes: the exchange of information with an external control device (for example, a microprocessor); information exchange with the control object; self test

In the first mode, information is exchanged between this device and the microprocessor through the device input-output group 63 of the device (Fig. 1).

In this case, after the device address is recognized by the decoder 12, its output signal is initiated by block 4

to

Since the microprocessor (K580IK80) is byte-wide, the exchange of hexadecimal codes is byte-by-byte, i.e. the hexadecimal code takes 7 seconds in two steps.

Therefore, only after receiving the lower -and high byte, the interrupt request signal is removed from the output 58 of register 10.

When information is output from the register 10 from the outputs 59, the status code of the device is issued through multiplexer 11 and further through the input-output unit 1 to the outputs 63 of the device.

In the second mode, information is exchanged between the device and the control object, as well as software installation and reset of block 10.

In this mode, the operation of the device is determined by the control word received through a group of inputs 63 from the microprocessor. The control word comes from the outputs 22 of block 1 (Fig. 1) to the block 2 for storing features and from the outputs 56 to the inputs of the register 9 of the channels.

20

25

In the format of the control word, the mode is at output 38 of which -sub-30 holds 8 bits. In the three junior signals, the reception and output of bits (TO, D1, D2) contain, respectively, at inputs 34 and 35 s, the information about the number, the reception register for the response time to the specified control object Pa or

the microprocessor operation forms the end of operation signal. This signal goes through the corresponding bit of the outputs 17 to the microprocessor and is perceived by it as an indication of the signal. Answer.

In addition, according to the indicated signals, signals are generated that control the block of registers 8, the state register 10 and the multiplexer 11 (Fig. 4).

When receiving information from the microprocessor, the data through inputs 63, input block 1 is written into the registers of block 8.

When data is transmitted to the microprocessor for analysis, they are sampled from the outputs 53 and 54 of the registers of block 8 through the multiplexer 11, its outputs 60 and the I / O unit to the outputs 63 of the device.

Exchange of information between the data. The device and microprocessor are implemented with hexadecimal codes. Moreover, in view of the fact that

ts

to

293739 4

Since the microprocessor (K580IK80) is byte-wide, the exchange of hexadecimal codes is byte-by-byte, i.e. the hexadecimal code takes 7 seconds in two steps.

Therefore, only after receiving the lower -and high byte, the interrupt request signal is removed from the output 58 of register 10.

When information is output from the register 10 from the outputs 59, the status code of the device is issued through multiplexer 11 and further through the input-output unit 1 to the outputs 63 of the device.

In the second mode, information is exchanged between the device and the control object, as well as software installation and reset of block 10.

In this mode, the operation of the device is determined by the control word received through a group of inputs 63 from the microprocessor. The control word comes from the outputs 22 of block 1 (Fig. 1) to the block 2 for storing features and from the outputs 56 to the inputs of the register 9 of the channels.

20

25

In the format of the control word with

interrupt mask trigger. These bits are connected to the outputs of the 22 I / O unit.

The DZ and D4 bits of the control word determine the number of the checked object of the control object. This information from outputs 56 of block 1 is recorded

in register 9.

The control word bits D5 and D6 are not used in this mode and are reserved.

The high bit D7 controls the generation of the signal of the monitoring object from the output 62 of the installation block 7. The value of the D7 bit signal is removed from the output 50 of the I / O unit 1.

The information enters the control object and is received from it in a sequential code.

In the third mode is carried out

device self-check without entering information into the control object. In this case, the unit 4 mode settings generated signals, defining the self-control mode,

51

A signal from the output 44 of the mode setting unit 4 in block 6 initiates the testing of the self-test mode. When this occurs, the transfer of information from the output of block 8 of registers to its input. In this case, after the end of the indicated rewriting of information, an interrupt request signal is generated at the output 58 of the register 10,

.To prevent the transfer of information of the self-control to the object in the channel register 9 (fig ,, t) using the control word are written down

whether, as a result, the inputs of the object are blocked.

The operability of the device is established by the presence of undistorted information in the registers of block 8 and the generation of a request signal interrupt: output 58 of register 10.

A feature of the device is that the listed modes can be performed by the device in a specific order.

Consider examples of the operation of the device in each of these modes.

 Reception of information by the processor from the processor is carried out as follows.

In the initial state, all the memory elements of the device blocks are reset to the initial state by a signal from the input 36 of the device.

Next, the device performs reception of information into the block 8 of registers. At the same time, the inputs 15 of the device (FIG. 1) send the following signal to the inputs of bits 61, the device’s own address, and to the inputs of 33 bits the job setting code , at input 35 enters the sipole Extraction from the microprocessor.

Therefore, in the device and in the case of identifying its own address, a decoder 2 is triggered, the output of which goes to the corresponding input of I / O unit 1 and prepares data for transferring them from inputs 63 to inputs 21 of input-output unit 1.

The inputs of the decoder 73 block 4 setting mode (f g, 5) in this case receives a set of signals. corresponding to the third set in Table 2, Poetomz, the decoder 73 issues a signal at the corresponding output level, (which enters through outputs 55 to JUDIN from the inputs of block 8..

0

five

thereby writing the low byte of information from inputs 21 to block 8 of the I / O registers

After writing to the register from the output 38 of the element 77 of the delay of block 4 (Fig. 5), the operation completion signal (or the response signal received in the description of the K580IK80 microprocessor) is output to the microprocessor. After receiving the specified signal, the microprocessor may, if necessary, disconnect from the device to interact with another device.

The signal is removed from the input 35 of the mode setting unit 4 (Fig. 1.5), whereby the signal at the output 38 also takes a zero value.

After receiving the low byte of information in the device, the high byte is received.

The reception of the high byte is the same as that of the low byte through input 63 of the device. The difference lies in the fact that in this case, the inputs of the decoder 73 of the mode setting unit 4 (Fig. 5) receive a set of signals corresponding to the fourth set of the table. 2

Therefore, the sixth bit of the output of the decoder 73 and its corresponding input of the block 8 of registers and the corresponding register are excited. 35 Further, the process of receiving information is completely analogous to that described above for ml of this byte.

Upon completion of receiving information from the device, the microprocessor can perform a self-test of the device, transfer information to the test object, or transfer information to the microprocessor for analysis. The order of operation of the device is determined by the control.

25

thirty

40

45

l With signals that come in

to the inputs of the device.

I

Information transfer to the microprocessor from the device through the outlets 63

performed in the following way.

The inputs 61 of the decoder 12 (figure 1) receives the corresponding address of the device. The output signal of the decoder 1 2 allows the operation of the decoder-7-ora 73 block 4 task mode

(figure 5), to the inputs 33 and 34 of which receives a set of signals corresponding to the first set in table 2. The second bit of the deshi output is energized.

712

 The florist 73, the signal from which through the inputs-outputs 37 enters the corresponding input of the register 10, which is set to zero and removes the signal from the output 58 of the device (Fig. 1).

In addition, the same signal from the second bit of the decoder 73 E (FIG. 5) through the outputs 37 of the mode setting unit 4 is fed to the corresponding input of the decoder 12 and thereby forms the following information transmission path: the outputs 54 of the register unit 8, multiplexer 11, outputs 60 multiplexer 11 (Fig. 1), I / O unit 1, an open signal from the output 20 of the element 75 OR (Fig. 5) of the mode setting unit 4, the outputs 63 of the device.

In the process of performing the described operation, a signal for terminating the operation at the output 38 of the device is also generated.

Similarly, the high byte is transmitted to the microprocessor. For this purpose, control inputs are received at the inputs 34 and 33 of the mode setting unit 4, which correspond to the second set in the table. 1. In this case, the third bit of the output of the decoder 73 (FIG. 5) is excited, which sets up the multiplexer 11 for transmitting data from the outputs 53 of the block 8 of the I / O registers.

A sequential combination of the two described device exchange modes with a microprocessor can be used to check the operability of blocks 1.4,8,11 and 12 of the device by transmitting the control code to the device and then returning it to the microprocessor for distortion analysis.

The design feature of the device that determines its field of application is the ability to interact with the microprocessor in two ways: by contact and by interrupt.

Consider the operation of the device in the verification mode of the control object.

This mode can be divided into two sub-modes: the transfer of information to the control object and the reception of a reaction code from the object.

In the mode of transferring information to the control object in the same way as described, the test action code from the microprocessor is received, and

eight

0

five

0

five

write it to block 8 I / O registers.

Next, the device receives the control word from the microprocess. Sora, which determines the order of further operation of the device: interaction with the object or the transition to the self-test mode.

The control word is adopted as follows.

The inputs 61 receive the corresponding address of the device, the inputs 33 - code 11, and the input 35 - the signal output information by the microprocessor, which corresponds to the sixth set in the table. 2

Accordingly, the seventh bit of the output of the decoder 73 of the mode setting unit 4 (Fig. 5) is excited. The output signal from the decoder 12 (Fig. 1) allows the transfer of information from the device inputs 63 to the outputs 21 of the I / O unit 1. The information from the outputs 21 of the I / O unit is distributed as follows: the signals from the outputs of the three lower bits 17 come from the outputs 21 of the I / O unit 1 to the corresponding bits of the inputs 22 of the characteristic storage unit 2 (Fig. 2), and the signals from the outputs of the third and the fourth bits of the control word come from the outputs 21 of the I / O unit 1 to the corresponding bits of the inputs 56 of the register 9.

one

In this case, a signal arriving at the input 49 of register 9, records the channel selection code of the control object into the register.

The decoder 66 block 2 (Fig. 2) is triggered in accordance with the table. 1 in such a way that its output signal records a unit in one of the bits of register 65, the content of which determines the number of the receiving register of the test object. From the outputs 24 of the register 65, this code arrives at the corresponding inputs of the imaging unit 3 (Fig. 4).

Q Simultaneously with the same

described by the mode setting unit 4, an operation end signal is generated at the output 38, which leads to a corresponding microprocessor response.

Further, the signal from the first two bits of the input 45 sets the lag or advance of clock pulses relative to the information ones.

0

five

0

 9,129

A generator 14 is then turned on, which generates clock pulses according to the timing diagram.

The trigger 93 of the synchronization unit 6 (FIG. 7) is set to one state by a signal from input 32, which is activated in the working state or the device self-monitoring state and removed after recording information in register 9 (FIG. 1). The generator 14 operates until the end of the formation of the exchange pattern and is turned off by the signal at the output 31 of the driver 3.

After the flip-flop 93 is installed in one state, element 99 AND (Fig. 8) is triggered, through which synchronization pulses begin to flow to the Johnson counter, assembled on flip-flops 94, 95 and 96.

Depending on the mode in which the device operates (the lag or advance of clock pulses relative to the information,

which is determined by the state of the synchronization unit 6 (Fig. 7), the first clock pulse from the output will be generated by the switch 82 of the generator 5 (Fig. 6) or after the trigger 96 is set to one (Fig. 7), or after it is set to one trigger state 96, i.e. on the second or third pulse from the output of element 99 And, respectively.

The next clock pulse produces the installation of flip-flops 94, 95 and 96 in such a state that the switch 81 of the driver 5 is activated. The output signal of this switch through the output 42 of the driver 5 is fed to the inverted input 42 of element 99 And thus prohibits the passage of clock switches. pulses through the element on the synchronous inputs of the triggers 94, 95 and 96.

In this state, the triggers 94, 95 and 96 are before the completion of the formation of the entire exchange pattern. The setting of these triggers to the zero state occurs by the output signal of the element 101, which is triggered by the signal of interrogating the response of the object from the output 31 of the driver.

The transfer of the selection code of the receiving register of the control object from the outputs 27 / of the register 3 (FIG. 4) is performed from the outputs 24 of the register 65 of the block 2 (FIG. 2) through

o

739

five

0

ten

And 70, 7Q, 70, and 70 elements (FIG. 4) of register 3 at the enable signal from input 48. This signal is the output signal of element 102 (FIG. 7), which is triggered by the first pulse from the output of trigger 94.

The output signal of the switch 81 is the enable signal for the operation of the element 88 And, which allows the arrival of the counting pulses at the input of the counter 78.

The counter 78 (FIG. 6) forms a sequence of fifteen pulses. Counter 78 provides a time exchange diagram of the exchange, controlled by switching signals from the outputs of register 3 (Fig. 4), with which it is connected to the outputs 40. After counting fifteen input pulses, element 84 is triggered, the output signal of which sets the trigger to one state.

79. in

The trigger 79 is set to one at the signal from the output of the switch 80 at the end of the first clock pulse and is in this state until the trigger 79 is set to one. The output signal of the trigger 79, sets the trigger 79 to the zero state through the element 90 RSHI. .

During this time (single state of the trigger 79), the corresponding elements of AND switches 82 and 83 are kept in the open state. At the same time, from the input 52 of the generator 5, through the switch 83, the output of the device 18 (FIG. 1) The ect, and from the output of the switch 82, so-called domestic pulses are output, which synchronize the reception of information pulses by the control object on the one hand, and on the other hand synchronize the signal supply to the output 52 of block 8 of registers and then switch 83

on the output 18 of the device (Fig. 1).

Fifteen first clock pulses are generated by the signal from input 39 of block 5 passing through switch 82 to the output.

After issuing the end-of-test output impulses from output 29 and polling the response of the object from the device’s outputs 28, the switch 71 of the driver 3, the output

the signal of which is fed to the input 30 of the imaging unit 5 (Fig. 6) and sets the trigger 79 to one state. In this case, a one-oscillator 91 is triggered, which, through element 89 OR, sets counter 78 to the zero state. In addition, the same signal sets the zero state to the trigger 79,. At the information input of the trigger 79, a zero signal is received from the trigger 79,... Therefore, after counting thirteen pulses by the counter 78, the trigger 79, the output clock signal of the element 84 is not set to one.

Next, the device enters the mode of receiving the reaction code from the control object. The reception of the reaction of the object is synchronized by clock pulses from the output of element 87 I, which is opened in this case by a signal from a single input of the trigger 79 ,. Clock pulses arrive at element 87 and from the start of an element

And 101. I

 Pulse count of reception cyclograms

the reaction code, as described, is carried out by the counter 78. After sixteen pulses are counted, the trigger is set to the zero state by a signal from the output of the counter 78. At the same time, the clock pulses at the output of the driver 5 through the element 87 I. and 96 signals from the output of the 31 generator trigger 93 block 6 synchronization. In addition, the output signal 43 of the one-shot 92 is set to one state by the register 10, which at output 58 generates an interrupt request signal, which is fed through the outputs 17 of the device to the microprocessor.

In operation, the element 85 and controls the decoder 72 of the former 3. The element 86 and generates a signal of the end of the issuance of the test effect on the object in the case when the clock pulses must be ahead of the information.

After the processor processes the interrupt signal, the reaction code is received into the microprocessor as described above. Further, if an unconditional diagnosis of the object is performed, then the object can be set to

five

0

five

0

five

0

five

0

five

 running condition. For this, a control word is received from the microprocessor through the inputs 63, in which the first, second and third bits are in the zero state, the fourth and fourth bits define the channel number in the control object, and the eighth bit is in the single state . The signal from the output of the eighth bit is fed to the inputs 21 of the I / O unit 1.

The installation unit 7 gives from impulse 62 an impulse for setting the object to the initial state.

To turn off the device, a signal is applied to the corresponding input of the generator 14.

In the self-test mode, as described above, a special control code is received and recorded in block 8 for checking the equipment of the device.

Then, a control word is received from the microprocessor similarly to the described one, which sets the self-control mode. In this word, the fourth and fifth bits are applied to register 9 ,. have a zero value. In addition, in the information arriving at the inputs 33 of the mode setting unit 4, there is a zero code. Therefore, in. according to tab. 1, the corresponding output of the decoder 73 will be excited. Next, as described, it is necessary to turn on the generator 14, after which the device begins to function as for the exchange mode with the control mode. The zero code in register 9 is perceived by the object as a ban on receiving information from the device.

The microprocessor can receive the code in the same way as has been described in order to analyze the performance of the device. If the received code is identical to the one transmitted to the device, then it is considered operable.

In this mode, the correctness of the formation of the clock and information pulses by the device can be checked. To check the formation of clock pulses, it is necessary to transmit to the device a code containing only units. When a clock pulse is missed, the corresponding bit of the converted control code will be zero.

Thus, in the self-checking mode, both the operability of the device's equipment for ensuring the storage of information and the implementation of the time diagram of work are checked.

This device has wider functionality than the known ones, since the design features of the device provide the possibility of its use in the hierarchy. system of control of multiple objects. In addition, it is possible to flexibly take into account the specifics of control objects by ensuring that information pulses are ahead or behind relative to clock pulses.

The device also allows for the efficient use of the microprocessor of the higher control level of the monitoring system by virtue of the fact that the design features provide interaction with the microprocessor in the multiplexing mode without busy modes.

Improving the reliability of the operation of the device is achieved due to the fact that the elements and connections of the device allow the implementation of a self-monitoring mode in which the operability of both the equipment that generates clocks and the equipment that generates information pulses is checked.

Claims (1)

Invention Formula A control device containing the first pulse shaper, two registers and an I / O unit associated with the I / O with information inputs / outputs of the I / O device — with the information inputs of the I / O register block, the bits for setting the output channel of the block — with corresponding the bits of the information input of the first register, the first control input with the first control output of the mode setting unit connected by the second control output to the first control input of the input / output register unit, the control of the mode of the second control output — to the control input of the first register; the third control outputs — to the first information inputs, the second register, the inputs; five Reception and Output - to the corresponding discharges of the control input of the device, characterized in that, in order to expand the functional capabilities of the device and increase the reliability of the control, a multiplexer, a decoder, a pulse generator, a synchronization unit, a block units, the second pulse generator, the attribute generation unit and the characteristic storage unit connected by the information inputs to the corresponding bits of the information input of the input-5 output registers block, the first information outputs the second information inputs to the second information inputs of the second register 0, the control input to the fourth control output of the mode setting block, and the installation input to the corresponding bit of the control input of the device and the inputs of the first register, the synchronization unit, the second pulse maker, the I / O register unit, and the installation unit associated with the first control input with the high-order discharge of the I / O unit stroke, second The second control is controlled by the input with the control input of the first register, the output with the corresponding control output of the device, and the information 5 inputs - with the output of the pulse generator, with the first information inputs of the second pulse shaper, and with the first information inputs of the synchronization unit, connected to the first control input to the first control, to its input of the sign forming unit and to the first control output of the first pulse shaper, first informational 45 outputs - to the first information inputs of the first pulse generator and to the second: information inputs of the second pulse generator, the second information outputs - to 50 third information inputs of the second pulse generator and to the second information inputs of the I / O register block, the control output to the second control input 55 of the control unit of the characteristic generator, the second control input to the corresponding bit of the second control output of the mode setting unit, the second informational hopper - to the second the information output of the formation of the signs, and the third control input to the first control output of the second pulse generator connected to the second control output with the control input. of the second register, the control outputs — with the corresponding bits of the control output of the device, with the second control signal of the first pulse generator, and with the first control outputs of the characteristic generating unit, the first discharge of the third control output — with the first control input of the input register output, the fourth control outputs — with the control inputs of the first pulse driver, the third information input — with the information output of the first pulse generator, the fourth information input inlet - with the first data output IO register unit and the output control - a control device and output a third data input registers & Input Unit o . five 0 da-output associated with the fourth information input with the information input of the device, and the second to the third information outputs - respectively. with the first and second information inputs of the multiplexer connected by the third information inputs to the first output of the second register, the control inputs. to the third control output of the mode setting block, and the output to the first information inputs of the I / O unit connected by the second information input to the depressor output and to the control input of the mode setting unit connected to the output. End of operation to the output of the Interrupt Request of the second register and to the information the output of the device connected by the address outputs with the second control outputs of the tracer and the outputs of the first register, and the corresponding bits control decoder and pulses. inputs - with inputs inputs of the generator Table 1 Fie.2 (rig. 3 (pt / e.J phage, 5 r (StCM Co  "S 45- c Editor 0. Petrushke Compiled by A.Lishansky Tehred L. Oleynik Proofreader S. Shekmar Order 388/54 Edition 673 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 b 5J Q.