RU2001452C1 - Device for checking memory units - Google Patents

Abstract

The invention relates to computer technology and can be used in the development of devices for monitoring RAM blocks. The purpose of the invention is to increase the reliability of the device by simplifying it. A device for monitoring memory blocks includes a control unit, an address setting unit, a test setting unit, a test set generator verified number generator, number register, bitwise comparison unit, error address determination unit. New in the device is the composition of control and address units and communication within these blocks and between device units. 3 ill.

Description

The invention relates to the field of computer technology and can be used in the development of devices for monitoring random access memory units, in particular, on semiconductor elements.

A device for monitoring memory units is known, comprising a test task unit, a control unit, a synchronization unit, an address setting unit, a bit comparison unit, and a number register. The main disadvantages of such a device are: a limited selection of tests and modes, which does not provide sufficient efficiency for monitoring memory units.

The closest in technical essence to the claimed device is a device for monitoring memory blocks, comprising a test task unit with an output test set generator, an address setting unit, a control unit, a read signal generator, a number register, a bit block comparing the definition of the error address.

The device provides monitoring of random access memory blocks using the Marsh, Diagonal tests for repeated or repeated tests and automatic switching of the voltage values of the memory chips (nominal, maximum, minimum).

A disadvantage of the known device is the complexity and inability to automatically determine the change of the test address with accuracy up to the bit, which does not allow setting the fault address accurately enough.

The aim of the invention is to increase the reliability of the device.

The indicated goal is achieved by that. that in the device for monitoring memory units containing a control unit, an address setting unit, a test setting unit, a test set generator, a verified memory unit, a verified number generator, a verified number register, a bit comparison unit and an error address determination unit, and the first and second information outputs of the address setting unit are connected to the corresponding inputs of the test task unit, the outputs of the test set generator are connected to the inputs of the test memory unit, the outputs of which are configured l checked emogo number connected to the data inputs of the first register, whose outputs are co-joined with those first inputs of block bit-wise comparison, the control unit includes a register control word ELAPSED frame counter small loop regeneration counter forming unit

write / read signals, the first, second and third multiplexers, the And element, and the ready trigger, and the address setting unit includes a base address counter and a current address counter, each of which contains N address setting triggers, a transfer forming unit, N selectors and N -digit counter, wherein the information input of the device is the information input of the control unit, the first, second, third, fourth, fifth and sixth control inputs of the device are respectively the first, second and third control inputs the control unit, the sync input of the test task unit, the clock register of the number register and the second control input of the address set unit, the first control input of the device is additionally connected to the sync input of the address set unit and the first sync input of the error address determination unit, the second control inputs of which are additionally connected to the second control to the input inputs of the device, the output of the error address determination unit is the first output of the device, and the fifth output of the control unit from the group of its control outputs is the second m output of the device, inputs of the signs of the end of the account of the control unit are connected to outputs of the signs of the end of the account of the address setting unit, the first outputs from the group of information outputs of the control unit are connected to the first inputs of the test set generator and the address inputs of the error address determination unit, the second and third outputs from this group the outputs of the control unit are connected to the first and second information inputs of the address setting unit, the fourth and fifth outputs from this group of outputs of the control unit are connected respectively with the fifth and sixth information inputs of the test task unit, the first, second, third and fourth outputs from the control output group of the control unit are connected respectively to the first control inputs of the address set unit, with the first, second and third control inputs test assignment unit and address assignment unit, the third and fourth information outputs of the address assignment unit are connected to the corresponding inputs of the test assignment unit, the first and second outputs of which are connected respectively to the second inputs of the ph the test device world, with its third inputs and second information inputs of the number register, in: the other outputs of which are connected to the corresponding inputs of the bitwise comparison block, the first and second outputs of which are connected respectively to the information and the recording permission input of the error address determination unit, the shift inputs of the register control word of the control unit, frame counter, small cycle counter and regeneration counter are combined and connected to the information input of the control unit, the first input from the group of second control inputs of the control unit is connected to the first clock inputs of the control word register, frame counter, small cycle counter and regeneration counter, and the second inputs from the group of second control inputs of the control unit are connected to shift enable inputs respectively of the control word register, a frame counter, a small cycle counter, and a regeneration counter, the first control input of the control unit is connected to the second clock inputs of the frame counter, a small cycle counter, and the sync inputs of the circuit no write / read signals and readiness trigger of the control unit, the third control input of which is connected to the second sync input of the regeneration counter, the inputs of the signs of the end of the count of the control unit are connected to the information inputs of the third multiplexer, the output of which is connected to the first input of the And element, the first, second and third the outputs of the control word register are the corresponding information outputs of the control unit, the fourth outputs of the register are connected to the information inputs of the signal conditioning circuit for write / read and the first multiplexer, the control inputs of which are combined with the control inputs of the third multiplexer and connected to the first outputs of the frame counter, the second output of which is connected to the second input of the AND element, the third input of which is connected through the inverter to the sixth output of the control word register, the fifth outputs of which are connected to the control inputs of the second multiplexer, the information inputs of which are combined with the corresponding first, second and third control outputs of the control unit and are connected to the outputs of the small cycle counter, the first outputs of the regeneration counter are the fourth outputs of the control unit, the output of the first multiplexer and the outputs of the write / read signal generating unit are its fifth information outputs, the output of the second multiplexer is the information input of the small cycle counter and inverse outputs of the AND element

connected respectively to the information input of the ready trigger and to the first input of the OR element, the second input of which is connected to the second output of the regeneration counter, the output of the OR element is connected to the fourth control output of the control unit, the output of the ready trigger is connected to the fifth control output of the control unit, 1 entrance from the first

0 group of information inputs of the address setting unit is connected to the S-input of the 1st trigger for setting the base address, the first and through inverters to the third input of the 1st selector of the base address counter, inverse

5, the output of the 1st trigger for setting the base address is connected to its D-input and the corresponding input of the first transfer shaping unit, the 1st output of which is connected to the V-input of the 1st trigger for setting the base address, the sync inputs and the R-inputs of N triggers for setting base addresses are combined and connected respectively to the sync input and to the second control input of the address setting unit, the inverse output of the 1st trigger

5, the base address setting is additionally connected to the second input of the 1st selector, the fourth input and inverse output of which are connected respectively to the i-th input from the second group of information inputs

0 of the address setting block and with the information input of the 1st bit of the base address counter, the first and second outputs of which are the first and second groups of outputs of the address setting block, the 1st input from the first

5 groups of information inputs of the address setting unit are connected to the S-input of the 1st trigger of setting the current address, the first and through the inverter to the third input of the i-ro selector of the counter of the current address, inverse

0 the output of the 1st trigger for setting the current address is connected to its D-input and the corresponding input of the second transfer forming unit, the 1st output of which is connected to the V-input of the i-ro trigger for setting the current address. the clock inputs and R inputs of N triggers for setting the current address are combined and connected respectively to the clock input and the second control input of the address setting block, the inverse output of the 1st trigger

0 setting the current address is additionally connected to the second input of the 1st selector, the fourth input and inverse output of which are connected respectively to the i-th input from the second group of information inputs

5 of the address setting block and with the information input of the 1st category of the current address counter, the first and second outputs of which are the third and fourth groups of outputs of the address setting block, the input -and the current address counter is connected to the source of the logical unit, the input +1 of the base counter the address is connected to the output of the counter end of the counter of the current address, the control inputs of the counters of the base and current addresses are connected to the corresponding first control inputs of the address setting unit, the third control input of which is connected to the input m blocking the counters of the base and current block addresses.

Technical solutions with a set of features similar to the set of distinctive features of the object of the invention are not available.

SUMMARY OF THE INVENTION that this set of essential features and the relationships between them allows one to obtain a simpler and, therefore, more reliable device that allows monitoring and reliable diagnosis of memory units using the tests Marsh, Gallop, Ping Long.

Thus, the proposed device has properties that are not inherent in known devices. This is explained by a new set of essential features and new relationships.

In FIG. 1 is a block diagram of an apparatus for monitoring memory units; in FIG. 2 is a diagram of a control unit; FIG. 3 is a diagram of the 1st category of counters of the base and current addresses.

The device comprises (see Fig. 1) a control unit 1, an address setting unit 2, a test setting unit 3, an input set driver 4, a verified memory unit 5, a verified number generator 6, a number register 7, a bit-by-bit comparison unit 8 , error address determination unit 9, information input 10 of the device, control inputs 11-1. ,, 11-6 devices, first output 12 and second output 13 of the device, inputs 14 of signs of the end of counting of block 1, information outputs 15-1 .. .15-5 and control outputs 16-1 ... 16-5 of control unit 1, the first inputs 17-1 and the second inputs 17-2 are informational , control inputs 18-1 ... 18-3 and clock input 19 of address setting block 2, information outputs 20-1, .. 20-4 of block 2, outputs 21 of the end of counting signs, information inputs 22-1 ... 22 -7, control inputs 23-1 ... 23-3 and sync input 24 of block 3 of the test task and its outputs 25-1 ... 25-2, inputs 26-1 ... 26-3 of the test set generator, its outputs 27, information inputs 28-1 ... 28-2 and clock input 29 of the 7th register, the first 30-1 and second 30-2 outputs of the 7th register, inputs 31-1 ... 31-2 of block 8 of the bitwise comparison , the first outputs 32-1 and the second output 32-2 of block 8, address inputs 33. information 34 inputs, input

35, write enable, first input 36-1 and second control inputs 36-2 of error address determination unit 9.

The control unit 1 (see Fig. 2) contains

control word register 37, frame counter 38, small cycle counter 39, regeneration counter 40, write / read signal generating unit 41-1, first 41-2 and second 42-1 and third 42-2 multiplexers, elements AND 43- 1 and OR 43-2 and the ready trigger 44, outputs 45-1 ... 45-6 of the control word register 37.

The address setting unit 2 contains an M-bit counter of the base address and an M-bit5 counter of the current address, performed in the same way. A typical counter circuit (see Fig. 3) comprises N address setting triggers 46, a transfer signal generating unit 47, N selectors 48 and an N0 bit counter 49.

The information input 10 of the device (see Fig. 1) is used to record source data into the device and is connected to the information input of the control unit 1. The first

5, the control input 11-1 of the device serves for supplying working clock pulses with a frequency of 2.5 MHz in the control mode of block 5 of the memory being checked and is connected to the first control input of block 1, the clock input 19 of block 2 and the first control input 36- 1 of block 9. The second control inputs 11-2 of the device are used to supply a clock and write enable signals in the recording mode of the source data to

5 register 37 and counters 38 ... 40 of block 1 and reading the results of control from block 9 in the mode of reading results and are connected to the second control inputs of block 1 and the second control input 36-2 of the block

0 9. The third control input 11-3 of the device receives a continuous series of working clock pulses with a frequency of 2.5 MHz to synchronize the counter 40 of the regeneration of unit 1. This series is not blocked when the device stops after the end of the control unit 5 of the checked memory. The input 11-3 of the device is connected to the third control input of block 1. The fourth 11-4 input of the device is connected to the clock input 24

0 of block 2 and serves to transmit clock pulses with a frequency of 10 MHz. The fifth input 11-5 of the device, connected to the clock of the register 7, receives a strobe for comparing the checked and the reference number. On the sixth 11-6 input of the device, a RESET signal is received to set the triggers 46 for setting the base and current addresses.

The first information outputs 15-1 of the control unit 1 are connected to the first inputs 26-1 of the driver 4 and the address

the inputs 33 of the block 9 determine the error address At the second information outputs 15-2 of block 1, a mask is fixed that fixes the specified bits of the test address in an unchanged value given by the signals installed on the third information outputs 15-3 of block 1. Outputs 15-1 and 15- 2 are connected respectively to the first and second information information 17-1 and 17-2 of unit 2. The fourth outputs 15-4 are connected to the fifth information inputs 22-5 of the address setting unit 3 and serve to supply a regeneration address. The fifth information outputs 15-5 are connected to the sixth information inputs 22-6 of block 3, and test data (D, WE, RAS and CAS) are set on them. The first control outputs 16-1 of block 1 are connected to the first control inputs 18-1 of block 2 and are used to supply control signals for the operation of the test address counters. The second and third control outputs 16-2 and 16-3 are connected to the first and second control inputs 23-1 and 23-2 of block 3, the control signals of the address and data switches of block 3 are set on them. The fourth control output 16-4 block 1, the output of the counter lock signal at the end of the test and during the regeneration time, is connected to the third control inputs 18-3 and 23-3 of blocks 2 and 3, respectively. The fifth control output 16-5 of block 1, the output of the interrupt signal, is the second output 13 of the device, the first output 12 of which is connected to the output of the address determination unit 9 and errors are used to display control results from the device

The information outputs 20-1 ... 20-4 of block 2 are connected to the corresponding information inputs 22-1 of 22-4 of block 3 and are outputs of the base address of the row, base address of the column, current address of the line, and current address of the column, respectively. The outputs 25-1 of the test address and the outputs 25-2 of the test data are connected respectively with the second, with the third inputs 26-2 and 26-3 of the driver 4 and the second information inputs 28-2 of the register 7. The outputs 27 of the test set of the driver 4 are connected to the inputs of the block 5 of the test memory, the outputs of which are connected via the former 6 to the first information inputs 28-1 of the 7th register. The outputs 30-1 of the verified and 30-2 reference numbers of the register 7 are connected to the inputs of the bitwise comparison unit 8. The results of the comparison with the inputs 32-1 of block 9 and the sign of the presence of at least one non-comparison from the output 32-2 are supplied respectively to the information inputs 34 and the recording permission input 35 of block 9

The shift inputs of the control word register 37 of the control unit 1 (Fig. 2). a frame counter 38, a small cycle counter 39, and a regeneration counter 40 are combined and connected to the information input 10 of the control unit 1. The first input from the group of second 11-2 control inputs of block 1

0 control is connected to the first clock inputs of the register 37 of the control word, counter 38 frames, counter 39 small cycle and counter 40 regeneration, and the second inputs from the group of second control inputs

5 11-2 of the control unit are connected to the shift enable inputs, respectively, of the control word register 37, frame counter 38, small cycle counter 39 and regeneration counter 40. To these inputs in the recording mode of the initial data, respectively, a clock input / output of information and signals enable recording in the corresponding register and counters of block 1. The first control input 11-1, input

5 clock pulses entering the device in control mode are connected to the second counter 38 frames, the counter 39 small cycles with the clock inputs of the circuit for generating write / read signals 41-1 and trigger 44

0 ready control unit 1. The third 11-3 control input of unit 1 is connected to the second clock input of the regeneration counter 40. The input 14 of the end of the control unit count signal is connected to the first input of element And. The first outputs 45-1, the second outputs 45-2 and the third outputs 45-3 of the 37 are the corresponding information outputs 15-1 ... 15-3 of block 1. The fourth outputs 45-4 of the register 37 are connected to

0 to the information inputs of the write / read signal generating circuit 41 1 and the first multiplexer 41-2. The control inputs of the multiplexer 41-2 are connected to the first outputs of the counter 38, the second output of which is connected to the second input of the And 43-1 element, the third input of which is connected through the inverter to the sixth output of the 45-6 register 37. The fifth outputs of the register 37 are connected to control inputs of the second

0 multiplexer 42, the information inputs of which are combined with the corresponding first 16-1, second 16-2 and third 16-3 control outputs of block 1 and connected to the outputs of the counter 39. The first

5, the outputs of counter 40 are the fourth information outputs 15-4 of block 1. The output of the first multiplexer 41-2 and the outputs of the write / read signal generating unit 41-1 are the fifth information outputs 15-5 of block 1.

The output of the second multiplexer 42 is connected to the information input of the counter 39, the direct and inverse outputs of the And 43-1 element are connected corresponding to the information input of the ready trigger 44 and with the first input of the OR 43-2 element, the second input of which is connected to the second output of the counter 40. The output of the element OR 43-2 is connected to the fourth control output 16-4 of unit 1, The output of the ready trigger 44 is connected to the fifth control output 16-5 of control unit 1.

On a typical circuit of the 1st category of the counter of the base (current) address, the i-th input from the first group of information inputs 17-1 of block 2 (Fig. 3) is connected to the S-input of the i-ro trigger 46 of the address setting, the first and through the inverter to the third input of the i-ro selector 48. The inverse output of the i-ro trigger 46 of the address setting is connected to its D-input and the corresponding input of the transfer formation circuit 47, the i-th output of which is connected to the V-input of the i-ro trigger 46, the sync inputs and R-inputs of N triggers 46 of the address assignment are combined and connected respectively to the clock input 19 and to the second control input house 18-2 unit 2 Address setting. The inverse output of the i-ro trigger 46 is additionally connected to the second input of the i-ro selector 48. The fourth input and the inverse output of the selector 48 are connected respectively to the i-th input from the second group of information inputs 17-2 of block 2 and to the information input i-ro yes, an address counter 49, the first and second outputs of which are the first 20-1 and second 20-2 for the base address counter, the third 20-3 and fourth 20-4 for the current address counter, by the groups of outputs of block 2. Input -I (it is marked in Fig. 3) the counter of the current address is connected to the source of logical units (FIG. 3 are not shown) entrance and base address counter connected (not shown) to the output of the terminal count of the counter of the current address. The control inputs of the counters of the base and current addresses are connected to the corresponding first control inputs 18-1 of block 2, the third control input of which 18-3 is connected to the blocking inputs of the counters of the base and current addresses of the block.

The device is intended for monitoring TEZs containing memory blocks with a capacity of 256 Kb - 11 MG6. Monitoring is carried out by comparing actual results with test reference values.

The monitored memory unit is implemented, for example, on a 565PT7 chip. The bit is informational and outputs, for example 10. Address inputs are ten-bit. The control inputs of the row entry are RASO ... RAS7. CASO ... RAS3 columns and WR write permissions.

The proposed device can be performed, for example, on a series of microcircuits 1500 or IZOOB.

The device works in conjunction with the PCME as part of the stand for monitoring logic blocks and memory blocks of the MVK. Verification is performed in start / stop mode. In one test run, one Russian microchip of the memory unit under test is tested.

Before starting the test in the dialogue mode, the operator - PCMU prepares the device for operation. Preparation includes:

- entry in the register 37 of the control word (see Fig. 2)

a) the number of the Rus circuit (outputs 45-1) of the tested memory unit 5;

b) a mask (outputs 45-2) that blocks those bits of the test address that must be clamped in the same position;

c) masks (outputs 45-3), which sets the clamped bits of the address to the log state. About or a log.

d) a mask (outputs 45-4), which allows to assign the value of the test background for each information bit of the test, and a diagram of one cycle of changing the test control signal WE;

e) a feedback number (outputs 45-5) for a small cycle counter;

e) a sign of disabling the device stop lock at the end of the test;

- write to the counter 38 the number of frames that make up the test to be launched;

writing to the counter 39 timing diagrams of the control signals of the base and current address counters, test address and data switches;

recording in the counter 40 regeneration time.

Presetting is performed when input control signals are input to inputs 1.1-2 of the device. Presetting of counter 40 is done once, before starting work. In the absence of control signals for installing the counter 40, a series of clock pulses are fed continuously from the input 11-3 of the device to its clock input until the device is turned off. The inputs 11-1, 11-4, and 11-5 of the series of clock pulses arrive in the absence of control input / output signals at inputs 11-2.

After the initial installation, the first working clock resets the ready trigger 44, and the Not ready for exchange signal appears at the output 16-5 of the unit 1 connected to the output 13 of the device. At the end of the test, trigger 44 is set to one. This signal blocks the supply of working clock pulses from the stand to the device inputs and notifies the PCM about the device’s readiness for dialogue.

Consider the operation of some device nodes in more detail.

The frame counter 38 is set to its initial state equal to the number of frames of the running test before starting work. For example, for the Marsh test, this number is 10 (binary code is 1010):

1. Record background (f);

2. Account from 1 to N, Th.Oe, zp.F;

3.Account from 1 to N. Th.F, zp.F;

4. Account from N to 1, Th.

5.Account from N to 1. Th.F, s.P.

6. Record of the inverse background (Ф);

7.Account from 1 to N, Th.F, sn.

8.Account from T to N, Th.F. ep F.

9.Account from N to 1, Th.F, sn.

10.Account from N to 1, Th.F., Zp.F.

After that, the counter 38 in the counting mode minus 1 counts to zero, changing its state according to the signal End of counting from the output of the third multiplexer 42-2, the presence of which, in addition, is one of the conditions by which the interruption of the device with the presence of signals: There is no stop lock by mistake and Zero frame counter.

The small-cycle counter 39 can generally be made in the form of a ROM from a counter. FIELD OF THE INVENTION A DEVICE for MONITORING BLOCKS OF MEMORY, comprising a control unit, an address setting unit, a test setting unit, a test set generator, a verified number generator, a number register, a bit comparison block and an error address determination unit, wherein the information outputs of the first and second groups of the address setting unit are connected to the corresponding inputs of the test setting unit, the outputs of the test set generator are information ion outputs of the device, the information inputs of which are the inputs of the verified number generator, the outputs of which are connected to the information inputs of the first group of the number register, the outputs of the first group of which are connected to the inputs of the first group of the bitwise comparison unit, characterized in that what, with the aim

com at the address inputs, in which the control signals for the counters of the base and current addresses of block 2 and the control signals for the switches of the test address and data of block 3 are recorded. The starting address for reading from the ROM is set before operation and corresponds to the test being started. The end of the small cycle is selected by multiplexer 42-1 from, for example,

three readings of the ROM address counter corresponding to the last word number in the ROM. related to the tests respectively Marsh, Gallop and Ping-Pong. With each cycle of working clock pulses from ROM

one word is read.

The regeneration counter 40 before starting work is set to a state corresponding, for example, 8 ms, which is stored at its inputs during operation

devices, and in counting mode, minus 1 counts to zero. The signal Zero of the regeneration counter is a signal to the beginning of the regeneration of the checked memory (the working clock pulses are blocked, and

the address switch of unit 3 is configured to transmit to the inputs of the unit a verified memory of the regeneration addresses) and connects the counter 40 to the counting mode plus 1. The verified memory is regenerated. By

at the end of the search for regeneration addresses, the counter 40 receives the source code. and everything repeats. The clock supply resumes, the device continues to operate.

(56) USSR Copyright Certificate No. 934553, cl. G 11 C 29/00, 1980.

USSR copyright certificate Ms 1444896, class G 11 C 29/00, 1986.

0

increase device reliability by

to simplify it, the control unit contains a control word register, a frame counter, a small cycle counter, a regeneration counter, a write / read signal generator, first to third multiplexers, an AND element, an OR element, and a ready trigger, and the address setting unit contains a base address counter and current address counter, each of which

Q contains N address setting triggers, a transfer former, N selectors and an N-bit counter, the information input of the control unit being the information input of the device, the first 5 B | m being the sixth control inputs of which are the first control input, respectively group inputs and the second control input of the control unit, the clock input of the test task unit, the clock register input of the number and the first

15 200145216

the control input of the address setting unit, the groups of which are connected to the first sync-first control input of the device, through the inputs of the control word register, is shared with the sync input of the setting unit of the address-counter of the frame, small cycle counter and ca and the first control input of the regeneration counter, enable addresses for determining the error address, the second up-shift of which is combined and connected the equalizing input of which is connected to the second control input of the group to the second control input of the device, control unit, the first control lane the output of which is the output of which is connected to the second sync blocks for determining the address of the error, the inputs of the inputs of the frame counter, the counter of little sign of the end of the count of the control unit. of the first cycle, with the clock inputs of the block, are connected to the outputs of the sign of the end of the formation of the write / read signals. the accounts of the address setting unit, the information of the first multiplexer and the trigger, the finished outputs of the first group of the control unit, the second sync input of the regeneration counter is connected to the inputs of the first grouping, connected to the second control driver of the test set and the address-input of the control unit, sign inputs the inputs of the unit for determining the address of the end of the account which are connected to the error, the information outputs of the second inputs of the third multi- and third groups of the control unit of the connection-plexor, the output of which is connected connected with the informational first input of the And element and the counting inputs of the first and second groups of the block for -20 D ° m of the frame counter, the outputs of the first, entering addresses, the information inputs of the third group of the register of the third and fourth groups of which is connected-controlling words are connected respectively with information outputs with transitions of the third and fourth groups of the block, the second and third groups of the test task unit, information inputs25 of the control, outputs of the fourth group of the test and sess of the second groups of which the control word registers are connected, respectively, are connected to the information output information inputs of the unit by the forms of the fourth and fifth groups of the control unit of write / read signals and information, controlling the outputs of the first, input inputs of the first multiplexer, the second and the third group of the control unit 30, the control inputs of which and the control are connected respectively to the control inputs of the third multiplexer by the loop inputs of the group of the address setting unit, are dined and connected to the outputs of the control group the input inputs of the first and second frame counter, the output of which is connected to the groups of the test task unit, the first control is connected to the second input of the And element, the third input of which and the second control-35 of which are connected via the inverter to the high input of the control unit of the address of the control register control words, coupled and connected to the first unit of the fifth group of which are connected to the equal output of the control unit, the control inputs of the second multi-second control output of which ow-plexer, the information inputs of which are the second output m devices, inputs and control outputs of the first, second second groups of the test driver and the third group of the control unit are connected to the outputs of the first antenna and connected to the outputs of the group counter of the test task unit, the outputs of the small cycle, the outputs of the group counter of the group of which connected to the output-generation connected to the information of the third group of the shaper outputs of the fourth group of the control unit. the set and information information, the information outputs of the fifth inputs of the second group of the number register, whose groups are connected to the output, the moves of the second group of which are connected by the first multiplexer and the block outputs by the inputs of the second group of the bit-CQ block of write / read signals formation, comparison, group outputs and the output, the co-output of the second multiplexer is connected to which are connected respectively to the synformation inputs of the small counter with information inputs and a single-cycle input, direct and inverse outputs of the recording elec- definitions of the address AND are connected respectively with the error error, in the control unit are shift 55 with the NEW input of the ready trigger and with the inputs of the control word register, the count is the first input of the OR element, the second frame chick, the counter of the small cycle and the input count of which is connected to the output the regeneration counter is combined and the regeneration connection, the output of the OR element is connected to the information input of the unit is connected to the first control output of the equation, the first control input of the control unit, the second control

the output of which is connected to the output of the ready trigger, in the address setting block The 1st information input of the first group of the address setting block (where II, N) is connected to the S-input of the 1st trigger of setting the base address, to the first and through the inverter to the third inputs of the 1st selector of the base address counter, the inverse output of the 1st trigger for setting the base address is connected to its D-input and the corresponding input of the first shaper, the first output of which is connected to the V-input of the 1st trigger for setting the base address, sync - rovers and R inputs from the first to N trig The base address ditch is combined and connected respectively to the clock input and the first control input of the address setting unit, the inverse output of the 1st base address setting trigger is connected to the second input of the 1st selector, the fourth input and the inverse output of which are connected respectively to the i-th information input the second group of the address setting unit and with the information input of the 1st category - the counter of the base address, the outputs of the first and second groups of which are connected to the outputs of the first and second groups of the address setting unit, the 1st information input the first group is connected to the input of S- 1st trigger specifying the current address, to the first input and through an inverter to the third input of the 1st counter selector those

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current address, the inverse output of the 1st trigger for setting the current address is connected to its D-input and the corresponding input of the second transfer former, the 1st output of which is connected to the V-input of the 1st trigger for setting the current address, clock inputs and R inputs from the first to N triggers, the current address settings are combined and connected respectively to the clock input and to the first control input of the address setting unit, the inverse output of the 1st trigger of the current address setting is connected to the second input of the 1st selector, the fourth input and the inverse output of which They are connected respectively with the 1st information input of the second group of the address setting unit and with the information input of the 1st category of the current address counter, the first and second outputs of which are connected to the outputs of the third and fourth groups of the address setting unit, the counting input of the current address counter is connected to the input logical unit of the device, the counter input counter of the base address is connected to the output of the counter end of the counter of the current address, the control inputs of the counters of the base and current addresses are connected respectively to the control input E group specifying unit addresses, a second control input of which is connected to the inputs of counters lock base and the current address.

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