SU972514A1 - Device for checking received data - Google Patents

Description

The invention relates to computing and can be used for readable from machine media (e.g., punched tape, magnetic tape) and peeled through computer equipment in a computer.

INFORMATION ..

A device for controlling received information is known, which contains a group of receiving registers and a majoritarian element, the device's information input connected to the inputs of registers, a. their output is with a mezhrititararny element C-- The disadvantage of this device lies in its complexity. Since the decision by the quarterly block requires at least threefold reception of information, which on the one hand complicates the device, and on the other reduces its speed

The closest to the proposed. in its essence, an error detection and correction device containing a parity control unit: parity, registers, a decoder, an EXCLUSIVE OR circuit, a syndrome generator, a double error detection device, a verification device, a single error detection device, AND ..

A disadvantage of the known device is the limitations of the correction function, which reduces only to correcting a single error, and the complexity of the design.

The purpose of the invention is to increase the effectiveness of controlling information by being able to correctly enter information in the presence of any

10 instances in one of the words of the pair and even with a constant distortion of information of one bit, including the control. For example, if you have a wrong record or find one

15 tracks of punched tape or magnetic tape, in case of failure of one channel (corresponding to one bit) during parallel transmission, information on wires, application of predicted information transmission on wires, application of the proposed system allows to recover information without error.

The goal is achieved

25 in that the device for monitoring the received information, containing the first and second registers, the first, the control unit for evenness, the first and second elements AND, the information inputs of the device being connected to the information and inputs of the first and second registers, the outputs of the first register connected to the informational inputs of the first parity check block, the device synchronization input is connected to the first inputs of the first and second elements AND, whose outputs are connected to the control inputs of the first and second registers, respectively the second block of control on even-numbered, block of comparison, the first and second elements of AND-NOT, the switch, the third element AND, the OR element, the delay element and the trigger, and the inputs of the initial installation and synchronization of the device are connected, respectively, to zero and counting the trigger inputs, the unit and zero outputs of which are connected to the second inputs of the first and second elements AND, the output of the second element, respectively, are connected to the output of the delay element, the output of which is the synchronizing output of the device, and All information bits of all information bits, except the control second register, are connected to the inputs of the second parity check unit, with the first group of inputs of the switch and the comparison unit, the single check output of the second register, is connected to the control input of the second parity check block, the outputs of all information bits, except the check bit of the first register, are connected to the second group of inputs of the switch and the comparison unit, the output of which is connected to the first inputs of the first and second About the NAND elements, the third AND element and the OR element, the output of the first parity check block is connected to the second inputs of the third AND element, the OR element and the first NAND element whose output is connected to the first control input of the switch, the output of the second control block by the parity is connected to the third inputs of the third element AND, the element OR and the second input of the second. The NAND element, the output of which is connected to the second control input of the switch, the group of information outputs of the switch, the outputs of the third AND element and the OR element, are respectively a group of information, the first and second control outputs of the device. The device assumes that each information word is written two times: once in the forward code, the second in the additional one for pro- parity checking, and each word has a check bit (for example, 7, 00000111. SEC) 1 st byte 2 nd byte; The drawing shows a device for monitoring received information. The device contains a trigger 1 count words, the first 2 and second 3 elements And, the first and second registers 4 and 5, the first and second 6 and 7 parity check blocks; delay elements 8, block 9 comparison, switch 10; the first 11 and second 12 elements are NAND, the third element is AND 13 and the element OR 14. The setup input of the device is connected to the input Installation in About the trigger 1. The device sync input is connected to the counting input of the word 1 trigger 1 and the inputs of the first and second AND 2 elements and 3, Single and zero outputs of the trigger 1 The first word and the second word are connected respectively to the inputs of the first and second elements And 2 and 3. The output of the element And 2 is connected to the C-inputs of the triggers of register 4, and the output of the second element And 3 is connected to C- the inputs of the trigger register 5 and the input ele cient 8 delays, the output of which is connected at the output of the synchronization device, the gate input of information to the computer after a control. Information inputs, including the input of the test bit, are connected in parallel to the D-inputs of the trigger registers 4 and 5. The unit outputs of the trigger information of the register 4 (all but the control bit) are connected to the inputs of the parity 6 of the first word parity, the inputs of the comparison unit 9 and the information input of the switch 10. The zero outputs of register 5 (all but the check bit) are connected to the inputs of the second parity block 7 of the second word, to the inputs of the comparison block 9 and the information inputs of the switch 10. Unit outputs the check bits of registers 4 and 5 are connected to the inputs of blocks b and 7 of the parity check respectively. Outputs The parity error of parity blocks 6 and 7 of the parity check is connected to the inputs of the first and second elements AND-NOT 11 and 12, the inputs of the third element AND 13 and the element OR 14. The output does not equal the comparison unit 9 also connected to the inputs of the elements AND-NOT 11 and 12, the input of the third element AND 13 and the input of the element OR 14 The outputs of the elements AND-NO 11 and 12 are connected to the control inputs of the switch 10, the outputs of which are connected to the information outputs of the device. The outputs of the elements AND 13 and OR 14 are connected to the control outputs of the device, respectively, to the outputs Fatal error and Error. The device works as follows. Before the start of the arrival of the information pulse, the setup impulse from the input. The initial reset arrives at the input. Setting in O of trigger 1 and resets it. The synchronization impulse that is generated, whether at the synchro path reading, for example, when working with punched tape, or using a special circuit that provides mandatory clocking of each information word, goes to the counting input of the trigger 1 word counting and to the inputs of the first 2 and second 3 elements I. Signal The first word from the output of the single trigger 1 sets the second input of the first element I 2, allowing the playback clock to pass from the output of the first element 2 to the pulse C inputs of the register triggers 4 and, recording the first word in the register 4, received from the group of information inputs of the device, including the control bit input, on the potential D-inputs of the trigger registers 4 and 5. Signal The second word from the zero output of the trigger 1 is fed to the second input of the second element 3, allowing the playback synchronization pulse to pass from the output of the second element 3 to the pulse C inputs of the triggers of register 5 and ensuring that the second word of information is written to the register 5, which comes from the information inputs of the devices a, including the check bit, to the potential D-inputs of the triggers of registers 4 and 5. In addition, the pulse from the output of the second element I 3, accompanying the second word of information, through the delay element 8 goes to the device output and provides strobirovanie and input information in the computer after control. The signals from the single outputs of the information triggers (all except the check bit) of register 4, containing the first word, are fed to the inputs of the control block b, the inputs of the comparison block 9 / information inputs of the switch 10. The signal from the zero outputs of the information triggers (all in addition to the check bit) of register 5, which contains the second word, is fed to the inputs — the parity block 7 of the second word, the inputs of the compare block 9, and the inputs of the switch 10. The signals from the single output of the check bit of registers 4 and 5 arrive respectively Correspondingly to the inputs of blocks 6 and 7 of the parity check. The signals of the Evennet error from the outputs of blocks 6 and 7 of the parity check control to the inputs of the first and second elements AND-NOT 11 and 12 of the inputs of the third element AND 13 of the match and the element OR 14. The inputs of the same elements 11-14 receive the signal Not equal to output of block 9 comparison. The signals from the output of the AND-HEY elements 11 and 12 arrive at the control inputs of the switch 10, permitting the passage of the first or second word, respectively, through the switch 10 to the information outputs of the device. The signals from the output of the third element H 13 and the element 14 OR arrive at the output of the device, respectively Fatal error and Error. The information bits of the first and second words complement each other (the second word is formed by inverting the information bits of the first word and adding a check bit, which is equal to the check bit of the first word). If both words, the first and the second, or at least their information bits, are read correctly, even with errors in the control bit, on. the output of the comparison block 9 does not have a signal Not equal and the signals from the outputs of the AND-HEY elements 11 and 12 allow the passage through the switch 10 to the output information buses of the information signals of this word pair. If the contents of register 4 of the first word are not equal to the inverted contents of register 5 of the second word, for example, in the case where one of the information tracks is constantly not read due to a fault in the input device, and the corresponding information bit is missing in both the first and second information word, signal, not equal to the output of block 9 compared, nor opens the elements AND NOT 11 and 12, prohibits the passage through the switch, 10 of the information word, which has a parity error. In this case, the element And 13 will work, which generates an error signal at the block output, indicating the presence of an error in one of the words or in both. If a parity error is detected in both words when two words are not compared, the signals at the output of the switch 10 will be absent, i.e. information is lost, since prohibitive signals will be sent to both control inputs of the switch, in this case, the elements AND 13 and the element OR 14 will work and the device will send signals to the Unrecoverable error and Error, which indicates that the information does not respond recovery. The use of a second parity check block, a comparison block, a first and second NAND element, a switch, a third AND element, an OR element, a delay element, and a tripleter greatly increases the efficiency

control, since there is a fixation of errors of any multiplicity in each individual received, and the correction of multiple errors in one of the received words.

Claims (2)

1. Tolstiky B.C. Detection and correction of shshbok in discrete devices. M., Soviet Radio, 1972, p. 260, Fig. 6.20. 2. For England 1319570, class G On F 11/08, 1973 (sheotype). m one ten // u: / J ± i 1 d