SU1399905A1 - Majority device - Google Patents

Abstract

The invention relates to automation and computing and can be used in digital multichannel systems. The aim of the invention is to expand the functionality due to the majorization of asynchronous information on the data buses of three-redundant channels. The device contains three redundant channels interconnected by inter-channel exchange networks, each channel has a data reception register, a data output register, a status word register, a desync interval register, a major block, a control block, a pulse counter, a trigger, a majority element, elements AND, OR, formers of single impulses. 2 Il. (L

Description

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The invention relates to automation and computing and can be used in digital multichannel systems.

The aim of the invention is to expand the functionality by providing majorization of asynchronous information on the data buses of three redundant channels.

FIG. 1 shows a block diagram of the majority device in FIG. 2, a functional diagram of one channel.

The majority device (Fig. 1) contains redundant channels 1.1-1.3, having input information buses 2.1-2.3, input buses 3.1-3.3 synchronization, output information buses 4.1-4.3, output buses 5.1- 5.3 synchronization, buses 6.1-6.3 of the control information , buses 7.1–7.3 of control information synchronization. The reserved channels 1.1–1.3 are interconnected via interchannel bus circuits (8.1–8.3) - (16.1–16.3).

FIG. 2 shows a functional diagram of one reserved channel 1.1 containing a data reception register 17, a data output register 18, a status word register 19, a desynchronization interval register 20, a majority block 21, a control block 22, a pulse counter 23, trigger 24, a majority element 25, elements AND 26 and 27, elements OR 28 and 29, shapers 30 and 31 single pulses, and a bus 32 clock pulses.

The device works as follows.

In the initial state, the pulse counter 23 and the trigger 24 are in the zero state. The register 20 of the dissynchronization interval contains a code corresponding to the permissible time of desynchronization of the channels of the AED, - the register 19 of the state word contains a single code, and its inverse outputs contain the zero code „Majority element 25, receiving signals O on the output also generates O, which prohibits the passage of clock pulses through the element 27 on the counting input of the counter 23 pulses.

The information received on the input information buses 2.1, is accompanied by a sync pulse on the input

The synchronization bus 3.1 is asynchronous. Therefore, for example, the reception and majorization of information is considered in the following two characteristic cases. Information on input information buses 2.1-2.3 appears with an interval from the first to the last synchronization pulse on the input buses 3.1-3.3 synchronization no more than cGr s.max 43 one of the input buses 3.1-3.3 synchronization; there is no sync pulse due to a fault or failure i.e. when one of the channels has no recording info 5

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Let the sync pulse come to the input bus 3.2 of the reserved channel 1.2. According to this pulse, information is received from the input information bus 2.2 into the data reception register 17, and the same pulse trigger 24 translates to a single state, resulting in one of the inputs of the majority element 25 of all reserved channels 1.1-1.3. the signals of these elements have not changed yet. With the arrival of a sync pulse on the bus 3.1 of the reserved channel 1.1, the trigger 24 of this channel is transferred to one state, as a result of which the majority elements 25 of all the reserved channels 1.1-1.3 trigger and on their outputs a signal

O changes to signal 1. In all reserved channels 1.1-1.3, a single pulse is formed at the output of shaper 31, which is used to write pulses into counter 23 from the register 20 of the code’s out-of-sync interval corresponding to the time of acceptable out-of-synchronization .r, v 1 at the output of the majority

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element 25 also allows the passage of clock pulses through the element 27 on the counting input of the counter 25 pulses. In this case, the pulse counter 23 does not have time to count to the last bit, since the pulse to the bus 3.3 arrives before the expiration of the Gras.Max time. At the same time, the trigger 24 of the reserved channel 1.3 is also set to one,; as a result, in all reserved channels 1.1-1.3 at the inputs of the majority element 25 and element And 26 there are single signals. At the output of element AND 26, a signal 1 appears, which passes through the element OR 28 at the input of shaper 30, at the output of which a single pulse of negative polarity is formed.

In all reserved channels 1.1-1.3, this pulse records information from the outputs of the majority block 21 to the data output register 18, the control information is written to the state register 19, and a pulse is output to the synchronization output buses 5.1-5.3. information from the register 18 output data on the output information busses 4.1- 4.3. Upon termination of the pulses at the outputs of the formers 30 of all the reserved channels 1.1-1.3, the flip-flops 24 return to the initial zero state. In this case, the outputs of the major elements 25 will be zero signals that prohibit the passage of clock pulses to the counting input of the counters 23 pulses. The device comes to its original state and is ready to receive the next information word on the input information buses 2.1-2.3.

Thus, for the case when information on input information buses 2.1-2.3 does not arrive simultaneously, but with a desynchronization time between the first and last incoming signals on the input buses 3.1-3.3 of synchronization, not exceeding 1 dss. The majorized information on the output information buses 4.1–4.3 is ready for output from the device after the last (third) pulse on the input buses 3.1–3.3.

If the information on the input information buses 2.1 and 2.2, accompanied by the sync pulse on the input bus 3.1 and 3.2 synchronization, enters the reserved channels 1.1 and 1.2 with the error time, the information on the input information bus 2.3 and the sync pulse on the input bus 3.3 synchronization is less ( due to a failure or malfunction of the source of information), then, similarly to that described when a sync pulse arrives on the sync input bus 3.2, the counter 23 impyJt) Cov records a code corresponding to

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 racesmax After THIS, the pulse counter 23 starts counting the clock pulses arriving at its counting input through the element 27 from the bus 32 clock pulses, and after time

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signal 1, which through the element OR 28 is fed to the input of shaper 30.

In all three reserved channels 1.1-1.3, at the output of shaper 30, a negative field pulse appears at the input to the record of the data output register 18 and the state word register 19. In this case, information from the outputs of the majority block 21 is recorded in the data output register 18, and information identifying the faulty situation is recorded in the register 19 of the state word. The presence of O in the first, second, or third bit of the register of the 19 state word indicates the absence of recording information in the reserved channels 1.1–1.3, respectively, and the presence of O in the fourth, fifth, or sixth bit of the register of the 19 word coc; incomparability of information, respectively, in reserved channels 1.1-1.3 with information in two adjacent reserved channels. If at least one is present at the inverse outputs of the register 19, the word of the state at the output of the element OR 29 appears a single signal, indicating the presence of control information on the 6.1-6.3 tires of the control information, which can be installed from the display means.

In all reserved channels, a negative pulse from the output of the imager 30 single pulses is also fed to the output buses 5.1–5.3 of synchronization and to the C input of the trigger 24.

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At the end of this pulse, the majorized information can be read by the receiver of information from the output information buses 4.1–4.3. In addition, both triggers 24 in the reserved channels 1.2 and 1.1 and, therefore, the entire circuit are returned to their original state, and the device is ready to receive the next information word.

The presence in the device of register 20 of the desynchronization interval makes it possible to easily adjust the operation of the device

at the time of permissible out-of-sync

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Claims (1)

Invention Formula The majority device, which in each of the three channels contains a trigger, has a single input connected to the sync input bus, and the information input is connected to the common bus, the trigger output is connected to the first inputs of the first element And the majority element, the output of the first element And is connected to the first input the OR element, the output of which through the first driver of single pulses is connected to the trigger input of the trigger, the second and third inputs of the first element I are connected respectively to the second and third inputs of the majority element, the pulse counter, the output of which is connected to the second input of the OR element, the second element AND, and the clock bus, is intended to expand the functionality by providing majorization of asynchronous information on the data buses of three redundant channels, A desynchronization interval register, a second single pulse generator, a majority block, a control unit, a data reception register, a data output register, a status word register, and a second OR element, n What is the trigger output connected to the first input of the status word register, the second and third inputs of which are connected respectively to the second and third inputs of the majority element, the output of the second element I is connected to the summing input of the pulse counter, the first and second inputs of the second element And are connected respectively to the clock bus and exit majority Q o 5 o five " 0 five element, which is connected to the pulse input of the pulse counter through the second shaper of the single pulse, the information inputs of which are connected to the output of the register of the desynchronization interval, the inverse outputs of the state word register are connected to the control information buses and through the second SH- element to the control information synchronization bus, information inputs the data reception register is connected to the input information buses of the channel, the recording input of the data reception register is connected to the channel synchronization bus, and you the data reception register moves are connected respectively to the first inputs of the control unit, to the first inputs of the majority block of this channel, to the second inputs of the major block of the previous channel and to the third inputs of the majority block of the subsequent channel, the outputs of the majority block of this channel are connected to the second inputs of the control block and to the information the inputs of the data output register, the input of which is connected to the input of the recording of the register of the state word, the output of the first driver of the single pulse and the output bus synchronization of the channel, the first input of the status word register of this channel is connected to the second input of the status channel of the previous channel and the third input of the subsequent channel status register, the output of the control unit of this channel is connected to the fourth input of the status word register of this channel, with the fifth input of the previous status word register and the sixth input of the predod channel state register, and the outputs of the data output register are connected to the output information buses of the channel. ) ici  S s. tv; -. "6 :: v S CN fvi ri 43