RU1833880C - Device for subscriber connection to trunk - Google Patents

Abstract

The invention relates to computer technology and can be used, in particular, for transmitting digital information. Over a transmission line. The goal is to increase the reliability of the transmission of digital information through the transmission line by eliminating the influence of the short circuit of the information lines of the transmission line. The device contains on the transmitting side input buses, a memory register, an inverter, a group of AND trunk elements, information bus lines connected to KN by subscribers who are receivers, each of which contains a group of AND elements connected to a power resistor, an output register, and output buses , In order to increase the reliability of the transmission of digital information through the transmission line, a control unit is entered on it on the transmitting side, and the element NOT, shift register, is entered in each of the N subscribers on the receiving side, the first, second, third buffer registers, the majority block, which ensure the exclusion of the influence of a short circuit in the information buses of the transmission line and the restoration of digital information. 1. s.p. f-ly, 3 ill. , (L

Description

The invention relates to computer technology and can be used to increase the reliability of transmission. Digital information on the transmission line in devices intended for use in highly reliable systems.

The goal is to increase the reliability of the transmission of digital information through the transmission line by eliminating the influence of the short circuit of the information lines of the transmission line.

In FIG. 1 shows a device for connecting subscribers to a trunk; figure 2 - control unit; Fig. 3 is one of a group of AND elements included in the control unit.

The device in figure 1 contains input buses 1, input register 2 memory, element AND NAND 3, write bus 4, group of elements 5, control unit 6, clock bus 7, bus 8 Ready, information bus 9 lines, the second group of elements And 10, the shift register 11, the second element OR NOT 12, the first 13, the second 14, the third 15 buffer registers, the majority element 16, the output register 17, the output bus 18, bus 19, subscribers 20, reset bus 21. In the control block there are (see Fig. 2) shifting counters 22, 23, 24, 25, groups of AND-NOT elements 26 ... 29 (see Fig. 3), AND elements 30 ..35, NOT elements 36. ..40, triggers RS 41, 42, elements OR00 W

with

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NOT 43, 44, output resistances 45 ... 50, state decoders 51, 52, 53, elements I-HE54, 55, 56,57,58, inputs 1, .. 4, inputs 1 ... 7, bus nutrition.

Groups of elements, conventionally highlighted in FIG. 2 by a dashed line, are assigned the names encoder 59 and switch 60.

The encoder includes the following elements: decoder 51, element I 30, 32 .., 35, elements OR 433, 44, elements 36, 37. The switch includes the following elements: output resistances 45 ... 50, groups elements AND-NOT 26 ... 29, elements AND-NOT54 ... 58.

The device operates as follows,

By the reset command, all the registers and triggers of the control unit (see figure 2) are set to the zero state,

To the input of the input memory register 2 (see Fig. 1) c. output bus 1 receives digital information and is written to the input memory register 2 at the trailing edge of the write pulse from the write bus 4. In this case, the control input of the input register 2 of the memory will receive permission for parallel recording of information ..

At the end of the write pulse at the control input of the input register 2, a positive potential will be set, allowing a sequential shift on register 2. The write pulse from the write bus 4 will also go to input 1 of the control unit 6, in which the RS-trigger 41 the leading edge of the pulse and allows the clock frequency from the input of the control unit 3 to pass through the And 31 element to the input from the shift counter 22. Moreover, the pulse width of the GEAP recording is selected less than the period Th.h. clock frequency. From the shift counter 22, through a group of elements And 26, the signals are fed to outputs 2, 3, 4, 5. The groups of elements And 26, 27, 28, 29 of the switch 60 are constructed identically from the set of AND-NOT elements (see Fig. 3), the output which is assembled according to the assembly OR circuit, is inverted and fed to. outputs 2, 3, 4, 5.

The signal from the output bus 3 of the control unit 6 on the trailing edge of the pulse inform. the matsi, entered in input register 2, passes through a group of elements And 5, information buses 9 of the transmission line, goes to all receivers 20, in each of which, after passing through a second group of elements And 10, it goes to the input of shift register 11, where it is written on the trailing edge of the pulse. Then, by pulses from the outputs 4, 5 of the control unit 6, information from the shift register 11 is entered into the buffer

registers 13, 14, 15, from the outputs of which information flows to the majority element 16, the output of which is fed to the output register 17. Moreover, in block 6

control from the output of the shift counter 22, the signal is fed to the S-input of the trigger 42, which is set to a certain state and generates a signal through the element 35 to the element OR NOT 44 in the encoder

59, generating a readiness signal and simultaneously blocking the shift counter 22.

The Ready signal signals to the control controller that subscribers5 are ready to start exchanging according to standard calls, accepted in the KAMAK standard, after which calls to the corresponding subscriber by applying a signal via Ni ... Nn buses.

0 Thus, in this mode, to transfer information from the input register of the controller to the output registers of subscribers, the control unit must sequentially issue the commands: Zap 2, Zap 3, Zap 4,

5 Zap 5.

When one of the information buses is short-circuited, the state decoder-51 is activated, made, for example, in the form of a 24-bit OR-NOT element,

0 in this case, a group of elements And 26 of the switch 60 is banned from passing signals from the offset counter 22 to the outputs 2, 3, 4, 5.

By the signal Record from bus 4, information from the control controller is entered into the input5 register 2 of the memory, and at the same time, control unit 6 is activated. The RS flip-flop 41 is on the leading edge of the pulse.

0 Clock frequency from input 3 in block 6

control will go through element And 31 on

input C of the shift counter 22. From the outputs of the shift counter 22 pulses

arrive at the RS flip-flop 42, which is set to a certain state and will give permission to the And 32 elements. 33, 34 of the encoder 59.

Thus, with a short circuit of one of the buses 9 of the transmission line to

At offset counter 22, a guaranteed delay is provided to provide protection against accidental failure.

On element And 32 there will be a coincidence of signals, and the first pulse of the clock frequency from input 3 of control unit 6 will arrive at input C of the counter shifting counter .5.

The biasing counter 23 operates as a control pulse distributor.

From the shift counter 23 through a group of elements And 27 of the switch 60 signals

arrive at outputs 1 ... 6. By the signal from output 2, on the trailing edge of the output pulse, the information recorded in the input register 2 of the memory passes through a group of elements And 5, information buses 9 of the transmission line and goes to all receivers 20, in each of which through the second group of elements And 10 falls on the input of the shift register 11, where it is recorded at the trailing edge of the pulse. -Then, the write pulse from the output 3 of the control block 6 information is transferred from the shift register 11 to the buffer register 13. After that, the next pulse from the shift counter 23 goes from the output 1 of the control block 6 to the shift input C 2 of the input memory register 2, according to the trailing edge of which the information recorded from the output buses 1 in the input register 2 of the memory is shifted by one bit,

The next pulse from the offset counter 23 will be output 2 of the control unit b. On the trailing edge of this pulse, information prepared on register 2 is written to shift register 11.

According to the next pulse from the shift counter 23 from the output 2, the information recorded in the shift register 11 is shifted in the opposite direction, after which the next pulse from the output 5 of the control unit 6 receives the information from the shift register 11, is transferred to the buffer register 14.

By the next pulse from the shift counter 23 from the output 1 of the control unit 6 to the input memory register 2, the information is shifted one more bit: the shift occurs along the trailing edge of the pulse. After that, again, according to the pulse from the output 3 of the block 6, the control on the trailing edge of the information prepared on the input register 2 of the memory is written to the shift register 11, and the next two pulses of the output 2 of the block 6 control shift the information recorded in the shift register 11. in the opposite direction by two bits.

By the next pulse from the output 6 of the control unit 6, the received information from the shift register 11 is transferred to the buffer register 15. In this case, according to the last pulse from the shift counter 23, a blocking pulse is generated for this counter and the HT signal is simultaneously generated at the output 7. The signal is Ready, as and in the case described above, signals to the control controller that the subscribers are ready to start

exchange according to standard circulation, accepted in the CAMAC standard,

Then, an appeal is made to the corresponding subscriber by applying a signal on the 5 nem Ni .., Nn signal.

Thus, in the event of a short circuit of one information bus of the highway for transmitting information from the controller's input register to the output registers of 10 subscribers, the control unit 6 must sequentially issue commands (see FIG. 2) 3ap 2, Zap 3, Sdv 1, Hall 2, Sdv 2, Zap 4, Sdv 1, 3sn 2, Sdv 2, Sdv 2, Zap 5, which provides restoration of digital information on 5 output registers of subscribers.

Figure 2 also shows a state decoder 52. The element is NOT 36, the element is AND 33, the offset counter 24, the group of elements is And 28, and the element is NOT 39 for the case when 0 two other bus lines are closed.

Decoder 52 states can be

made in the form of (gp-1) assembly of elements

SP1 (comparison chart) connected by

5 OR, where: m is the number of information tires

highways.

The operation of the device in this case occurs similarly to that recorded by control commands from the offset counter 0 24: Zap 2, Zap 3, Sdv 1, SDV 1, Zap 2, Sdv 2,. Sdv 2, Zap 4, Sdv 1, Sdv 1, Zap 2, Sdv 2, Sdv 2, Sdv 2, Sdv 2, Zap 5.

Thus, digital information is restored to the output 5 subscriber registers in the case of a short circuit of two bus lines of another

Figure 2 also shows a state decoder 53, an element HE 37, an AND element 34, a shift counter 23, a group of AND elements 29, and an HE element 40 for the case when two bus lines located relative to each other through one are closed. At the same time, control unit 6 sequentially issues the commands: Zap 2, Zap 3, Sdv 1, 5 Sdv 1, .Sdv 1, Zap 2, Sdv 2, Sdv 2, Sdv 2, Zap 4, Sdv 1, Zap 2, Sdv 2 , Add. 2, Add. 2, Add. 2, Rec. 5.

Thus, the restoration of digital information at the output registers of the subscribers is ensured in the case of a short circuit of the bus lines located relative to each other through one. The operation of the device in this case is similar to the operation of the device described in the case of a short 5 short circuit of one bus line.

Thus, the present invention improves the reliability of the transmission of digital information on the highway by eliminating the loss of transmitted information during short circuits of several information bus lines.

Moreover, the inventive device retains the ability to transmit digital information on the transmission line to subscribers with short-circuited buses in the transmission line, because identifies and corrects errors for various short circuit combinations in bus lines, i.e. Short circuit of one bus, two buses or two buses located through one.

The formula is invented and 1. A device for connecting subscribers to the trunk, containing on the transmitting side input buses connected to the information inputs of the memory register, the clock input of which is connected to the recording bus of the device and through the element NOT to the recording permission input of the memory input register a tee whose outputs are connected to the corresponding inputs of the elements AND groups whose outputs are connected through the information buses of the transmission line to the corresponding subscribers on the receiving side, and in each of them information the input inputs are connected to the corresponding bits of the information lines of the transmission line, the output register of each subscriber is connected to the corresponding output buses of the subscriber, the clock input of the output register is connected to the same bit of the address bus on the transmitting side, so that, in order to to increase the reliability of information transmission through the transmission line by eliminating the influence of a short circuit in the information buses of the transmission line, a control unit, information the busbars 1-1 ... 1-p of which are connected to the outputs of the elements AND groups, the enable input of the control unit is connected to the write bus of the device, the clock input of the control unit is connected to the clock frequency bus of the device, the reset input of the control unit is connected to the device reset bus , the first output of the control unit is connected to the shift input of the input memory register, the n-output of which is connected to the first information input of the input memory register, and the element HE, shift register, three buffer registers, majority input to each of the subscribers the first unit, the outputs of which are connected to data inputs of the output register, and inputs of a majority block connected to three respective outputs of the buffer registers, Informatsionnye inputs are merged

bit and connected to the corresponding outputs of the shift register, the N-output of which is connected to the first information input of the shift register, the input of the shift

which is connected via a highway to the second output of the control unit, the third output of which is connected to the control inputs of the group of AND elements on the transmitting and receiving side of the switch, and

0 in each subscriber is connected to the clock input of the shift register and through the element is NOT connected to the enable input of the shift register, the clock inputs of the first, second, third buffer registers

5 are connected through the trunk to the fourth, fifth and sixth outputs of the control unit, respectively, the seventh output of which is connected to the Ready device bus.

.0 2. The device according to claim 1, characterized in that the control unit comprises an encoder, four counters, two status decoders, three NOT elements, a switch, two triggers, an AND element, the input of a resolution of 5 or more connected to the installation input of the first a trigger whose output is connected to the first input of the And element, the second input of which is connected to the clock input of the unit, the reset input of which is connected to the inputs

0 reset of the first trigger, second trigger and counters from the first to the fourth inclusive, the bit outputs of the first counter are connected to the group of address inputs of the switch, the outputs of which are connected to the same outputs of the unit from the first to the sixth inclusive, the information inputs of which are connected to the information inputs of the first and second state decoders and with information

0 inputs of the encoder, the first output of which is connected to the first control input of the switch, the direct output of the second trigger: connected to the first input of the encoder, the second, third and fourth outputs of which are connected to the synchronization inputs of the second, third and fourth counters, respectively, and to the second, the third and fourth control inputs of the switch, the first, second and third of the group

0 information inputs of which are connected to the groups of bit outputs of the second, third and fourth counters, respectively, the outputs of the last bits of the second, third and fourth counters

5 are connected through the first, second, and third elements NOT to the counter resolution inputs from the second to the fourth, respectively, and also to the second, third, and fourth information inputs of the encoder, the fifth and sixth information inputs of which are connected to the outputs of both state decoders, respectively; the fourth encoder output is connected to the seventh output of the block, the output of the last bit of the first trigger, inverse to the second, is connected to the counter enable input, the counting input is to the output of the AND element and to the seventh

of the counter is connected to the output of the installation with the 5th input of the encoder.

the second trigger, the inverse output of which is connected to the enable input of the first counter, the counting input of which is connected to the output of the And element and to the seventh information

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