SU1059560A1 - Device for processor-memory interface - Google Patents

Abstract

1. A DEVICE FOR PAIRING A PROCESSOR, MEMORY, containing a control unit and an information control unit, the first inputs of which are connected to the device address input, the second, third inputs and the first, second and third outputs of the control unit are connected respectively to the reset and start inputs of the device and the control, sample and end of the device, and the fourth output - with the BTOfXJM input of the information control unit, the third and fourth inputs connected to the first and second information inputs of the device, respectively, and the first, Third, fourth and fourth outputs, respectively, with the outputs of the control signal of the address and information, the error correction signal, the information output and the output of the correction code of the device, characterized in that, in order to increase the reliability of information transfer and speed, the regeneration unit is entered into it, and a recording signal shaper, the first, second inputs and the first output of the regeneration unit being connected respectively to the second input, the fifth output and the fourth input of the control unit, and the second , the third and fourth outputs respectively to the first input of the address switch and the outputs of the error signals of the address and errors of the device regeneration period, the first input of the recording signal generator is connected to the sixth output of the control unit and the fifth input of the information control unit, the second and third inputs are respectively to the input the signal is the operation code of the device and the sixth input and the first output of the information control unit, and the output is with the output signal of the recording device, the second and third inputs of the address switch are connected respectively the seventh output of the control unit and the address input of the device, and the move with the address output of the device, the regeneration unit contains two comparison circuits, two timers, a convolution node, a regeneration address counter and a register, (L output of the first comparison circuit under | The key to the third output of the block and the first input of the register, the first input to the output of the register and the first input of the regeneration address counter, the output of which is connected to the second input of the register, the second output of the block and through the convolution node with the second input of the first cxebfii comparison, output The second comparison circuit is connected to the quad sided output of the block and the first to the timer inputs, the second inputs of which are connected to the first input of the unit, the output of the first timer is connected to: the first input of the second comparison circuit, the second input connected to the first output of the second timer, the second output which the second and third inputs of the regeneration address counter are connected to the first output and the first and second inputs of the block, and the control unit contains three AND-OR-NOT elements, two OR-NOT elements, shift register, trigger process litter, regeneration trigger, five delay elements, four NOT elements, four AND-NOT elements and a group of AND-OR-NOT elements, clicking the first inputs of the first and second elements

Description

AND-OR-NOT are connected to the third input of the block, and the outputs, respectively, with the information inputs of the shift register and the processor trigger, the first input of the third element, AND-ILINE, connect the fourth input of the block, the output with the information input of the regeneration trigger, the reset input. shift is connected to the second input of the block, and the first output to the first inputs of the first and second I-HB elements and through the first ale, | Delay ment with the fourth output of the block, the second input of the second AND-NOT element and the first input of the first OR-NOT element, output first The AND-NOT element is connected via the first element NOT to the second and third inputs of the second AND-OR-NOT element, the first shift register output is connected to the nepBOSwy input of the second ground OR-NOT input, the regeneration trigger output is connected via the second element NOT to the second inputs of the third and the first element AND-OR-NOT, the third input of which is connected via the third element NOT to the output of the processor trigger, the second output of the block, the second V111 inputs of the first and second elements OR-NOT and the first inputs of the elements ITILI-NOT groups and the third and fourth elements AND- NOT, exits which are respectively the fifth and seventh outputs of the block, the second output of the shift register is connected to the second input of the first AND-NOT element, the fourth and fifth inputs of the first AND-OR-NOT element and through the fourth element NOT and the second delay element to the second input of the third element AND-NOT and the third input of the third element AND-OR-NOT |, the fourth input connected through the third element ea. support to the output of the processor trigger, the output of the regeneration trigger is connected to the second input of the fourth element AND-NOT and the fourth input of the second element AND-OR-NO element, first and second outputs of the NOR lementov connected respectively .Through fourth and fifth delay elements with the third and sixth unit outputs, second and third inputs of AND-OR-NO groups are connected to the output

the second element is NAND, the fourth inputs form the first input of the block, and the outputs - its first output.

2, The device according to claim 1, 1 and 2, in that the information control unit contains an information register, a control code register, an information switchboard, a control code adder, two bitwise adders, a decoder number of the corrected bit, an error type decoder, and a parity check node, the output of the parity check node being the first output of the block, and the first, second, and third inputs of the first, fifth, and third inputs of the block, respectively; the first and second inputs of the check code register and information register are connected respectively with the fourth and second inputs of the block, and the outputs, respectively, with the first inputs of the first and second bit accumulators, the first, second and third inputs of the information switch are connected respectively to the output of the information register and the third and sixth inputs of the block whose first output is connected to the second input of the second bitwise adder, and the second output to the fourth output of the block and the second input of the first bitwise adder, the output of which is connected to the first input of the decoder t Error type, and through the decoder of the number of the corrected bit with the third input of the second bit accumulator, the output of which is the third output of the block, the second input of the error type decoder is the second input of the block, and the output of its second output.

3. The device according to claim 1, wherein the recording signal driver comprises an OR-NOT element and an AND-NO element, and the inputs of the OR-NOT element are respectively the first and third inputs of the shaper, and the output is connected to the first input an AND-NOT element whose second input and output are respectively a second input and an output of a mold.

one

The invention relates to a computational processor, in particular, devices for exchanging a processor with dynamic integrated memory, and can be used in communication processors.

There are known devices for interfacing the main memory, the processor, and the control and synchronization node, address registers, information registers, correction nodes, OR elements, output registers, and a switch. The disadvantage of these devices lies in their limited scope. The closest to the proposed technical entity is a digital storage device with self-control, containing a drive with an arbitrary Access Time, built on integral solid circuits, information control circuits and information characteristics generation, connected to data buses and addresses with a processor and with inputs and outputs storage device, input address formation schemes, input and output data formation schehenvl connected to the processor and storage device, and device control circuitry. The device allows, when writing to the memory, to add two address parity bits and information parity bits modularly to generate a common parity bit, which is remembered by the addressing cell, and then, when read, use this bit to control both data and hydro information 2. The disadvantages of this device are low reliability of the recorded information due to the lack of input control of address information and data, which may result in the need to reload the memory or correct the error, which will take considerable time and low speed, since the memory access starts after control bits. parity. The purpose of the invention is to increase the reliability of information transfer and device speed. The goal is achieved by the fact that a device containing a control unit and an information control unit, the first inputs of which are connected to the device address input, the second, third inputs and the first, second and third outputs of the control unit are connected respectively to the reset and start inputs of the device and the control, sampling and end of the device and the fourth output with the second input of the information control unit, the third and fourth inputs connected to the first and second information inputs of the device, and the first, second , the third and fourth outputs - respectively, with the output control signal 1 of the address control signal and information, the error correction signal, the information output and the output of the device correction code, the regeneration unit, the address switch and the recording signal shaper are entered, the first, second inputs and the first output of the block regeneration is connected to the second input, the fifth output and the fourth input of the control unit, respectively, and the second, third and fourth outputs, respectively, to the first input of the afvpeca switch and the error signal outputs ad During the device and the device regeneration period errors, the first input of the recording signal generator is connected to the sixth output of the control unit and the fifth input of the information control unit, the second and third inputs to the signal input, the operation code of the device and the sixth input and the first output of the information control unit, and EXIT with the output signal of the device record, the second and third inputs of the address switch are connected respectively to the seventh output of the control unit and the device’s address input, and the output to the address output of the device, and The regeneration block contains two comparison circuits, two timers, a convolution node, a regeneration address counter and a register, with the output of the first comparison circuit connected to the third output of the block and the first input of the register, the first input to the output of the register and the first input of the regeneration address counter whose output is connected with the second input of the register, the second output of the block and through the convolution node with the second input of the first comparison, the output of the second comparison circuit is connected to the fourth output of the block. and with the first inputs of the timers, the second inputs of which are connected to the first input of the block, the output of the first timer is connected to the first input of the second comparison circuit, the second input connected to the first output of the second timer, the second output of which and the second and third inputs of the regeneration address counter are connected respectively to the first output and the first and second block inputs, and the control block contains three AND-OR-NOT elements, two OR-NOT elements, processor shift / trigger register, regeneration trigger, five delay elements, four NO elements, The element of the element AND-НЁ and the group of elements is AND-OR-NOT, the first inputs of the first and second elements AND-OR-NOT are connected to the third input of the block, and the outputs are respectively to the information inputs of the shift register and trigger processor, the first input of the third element AND-OR-NOT is connected to the fourth input of the block, and the output is connected to the informational input of the regeneration trigger, the reset input of the shift register is connected to the second input of the block, and the first output is connected to the first inputs of the first and second elements AND-NOT and through the first delay element fourth exit block , the second one is the input of the second element NAND and the first input of the first element OR NONE, the output of the first element NAND is not connected to the first element NOT to the second and third inputs of the second element AND OR OR, the first output of the shift register is connected to the first the input of the second element OR NOT, the output of the regeneration trigger is connected via the second element NOT to the second inputs of the third and first elements AND-OR-NOT, the third input of which is connected via the third element NOT to the processor trigger output, to the second output of the block ;, the second inputs first and second elements OR-NOT and the first inputs of the elements AND-OR-NOT groups and the Third and Fourth elements AND-NOT, the outputs of which are respectively the fifth and seventh outputs of the block, the second output of the shift register is connected to the second input of the first AND-NOT element, the fourth and In addition to the inputs of the first AND-OR-NOT element AND through the fourth element NOT and the second delay element to the second input of the third AND-NOT element and the third input of the third AND-OR-NOT element, the quarter input connected through the third delay element to the processor trigger output trigger output regener connected to the second input of the fourth AND-NOT element and the fourth input of the second AND-OR-HB element, the outputs of the first and second OR-NOT elements are connected via the fourth and fifth delay elements respectively to the third and sixth outputs of the unit, the second and third the inputs of the AND-OR-NOT groups are connected to the output of the second AND-NOT element, the fourth inputs form the first input of the block, and the outputs - its first output.

The information control block contains the information register, the control code register, the information switch, the control code adder, two bit adders, the decoder of the corrected bit number, the error type decoder and the parity node, and the output of the parity node is the first output of the block, and the first, second and third inputs are respectively the first, fifth and third inputs of the block, the first and second inputs of the register of control codes and the information register are connected respectively to the fourth and second inputs of the block, and the outputs, respectively, with the first inputs of the first and second one-bit adders, the first, second and third inputs of the information switch are connected respectively to the output of the information register and the third and sixth inputs of the block, and the output - to the adder

the control code, the first output of which is connected to the second input of the second bit (CytviMaTopa, and the second output to the fourth output of the block and the second input of the first bit rank adder, the output of which is connected to the first input of the error type decoder and through the decoder of the number of the bit being corrected the third input of the second bit accumulator, the output of which is the third output of the block, the second input of the error type decoder is the second input of the block, and the output is its second output.

The recording signal generator contains the element OR-H; 3 and the element NAND, the inputs of the element OR NONE being the first and third inputs of the generator, respectively, and the output is connected to the first input of the element NAND, the second input and output of which are the second input and output of the shaper.

Fig, 1 shows the block diagram of the proposed device; in fig. 2 is a timing diagram of a reading and regeneration cycle in FIG. 3 - the same recording cycle; Figures 4-7 are functional diagrams of a control unit, a recording signal generator, an information control unit, control units for correcting errors and uncorrectable errors.

The device contains a memory (accumulator) 1, a regeneration unit 2, a control unit 3, an information control unit 4, a switchboard 5, a shaper, a write signal generator 6.

The regeneration unit 2 contains a regeneration address counter 7, a register 8, a convolution node 9, a first comparison circuit 10, timers 11 and 12, and a second

Scheme 13 Comparison

I

FIG. 1 denotes entry bus 14, drive, input bus 15 of the START signal, output bus 16 of the control signals, output bus 17 of the sample, bus 18 and 19 of the read and write strobes of the number, output address control of the 20 during write (read) and information during writing, input bus 21 of the end of operation signal, output bus 22 of the write signal, first input information bus 23, output bus 24 of the memory end signal, input bus 25 of the reset signal, bus 26 of the regeneration request signal, bus 28 and 282 error signals errors of the regeneration period, bus 29 of the control signal of the switch 5, bus 30 of summing up the counter unit 7, output bus 31 of the correction code bits, second input information bus 32, output bus 33 of error correction signals, output information bus 34. In FIG. 2, time is indicated delays in the occurrence of information on the leading edge of the pulse on bus 16; the delay time T of the write pulse relative to the leading edge of the pulse on the bus 16; input information (bus 23) U in; information at the output of the storage element Ugj,;,; information recording signal (bus 22} VU B. Control unit 3 (Fig. 4) contains AND-OR-NOT 35-37 elements, OR-NOT 38 and 39 elements, shift register 40, processor trigger 41, regeneration trigger 42 , elements (trigger ger) 43-47 delays, element., AND-NO 48, elements NOT 49-52, elements AND-NOT 53-55, and elements AND-OR-NOT 63 groups. Shaper 6 digsha record holds (FIG 5) the element OR-NOT 64 and AND-NOT 65., Block 4 control information soda 4KIT (Fig. 6) information register 66 register 67 control codes, information switch 68, adder 69 to the rolling code, bit accumulators 70 and 71, decoder 72 n of the corrected bit omer, an error type decoder 73, including a wave 74 of the control of the corrected errors and an error correcting node 75, and a parity check node 76, including the address control screwdriver 77 and a check convocation check circuit 78 of the recorded information. and 75 controls contain (FIG. 7) elements HE 79-85, elements AND-HE 86, element HE 87, element AND-HE 88, elements 89-94 of the addition of two bits modulo two, delay trigger 95 and element AND- NOT 96. FIG. 4-7, the 97 bit of the correction code for the read code and the sync bus 98 are indicated. The device operates as follows. After receiving the START signal on bus 15, in block 3, signals are generated that start MEMORY 1 on buses 16 and 17. At the same time, the address on bus 14 without waiting for the result of the input control in block 4 via switch 5, controlled by a signal. 1, the Control word bits, i.e., the code of the control word, on bus 21 and the address with check bits on bus 14, as well as the input information with check bits (during recording) on bus 23 are monitored in block 4, the control signal pin 20 is fed to fo1 "rover 6 where it blocks, in the event of an error, drove over bus 22 if a write operation is in progress. The control signals for the write (read) and input information for the write are output to the processor via the bus 20. The number write gate enters the imaging unit 6 via the bus 19 and is generated with a delay Tj (Fig. 3). When the number is written to memory 1, the input information in block 4 on bus 31 produces bits of the correction code. An example of the implementation of block 4 (Fig. 5) is given for the case of a correction code, however, if necessary, a control circuit with a correction code can be replaced by a modular control circuit with storage of check bits in memory 1 and subsequent reading control, since the method control reading can be anything. The time spent on the formation of test bits, in this implementation, does not introduce a time delay in the execution of the write operation (FIG. 3). When reading information on bus 32 from memory 1, the bits of the number and the correction code are written to register 66, controlled by a signal from block 3 via bus 18 and in block 4. In the case of a single error, the bits of the number are corrected. Since the processor has received a parity byte format, in block 4, the format of the read information is converted and parity bits are output to the processor. Corrected, rectified, and uncorrectable error signals are output to the processor via bus 33. Upon completion of the time diag.MNM, the memory end signal on bus 24 is output to the processor. Consider the operation of the device for the regeneration of information in the absence of a START signal on bus 15. The regeneration signal from timer 12 is supplied at a time interval defined by timer 12 on bus 26 to block 3 and starts a regeneration timing diagram. Via bus 30, a signal is added to add 1 to counter 7. Under the control of the zero signal via bus 29, the regeneration address from block 2 via bus 27 is preliminarily connected via switch 5 to the inputs of accumulator 1. From block 3 via bus 16 to control 1 are issued control signals . The sampling signal on the bus 17 during the regeneration work has a single level. The start of the Time Chart on the START signal is blocked until the regeneration is complete. When a regeneration address is detected, which is detected by register 8, node 9 and comparison circuit 10, overwriting the current value of the regeneration address from counter 7 to regx 8 is blocked by a signal from the output of comparison circuit 10 and address rewriting from the register 8 to counter 7 seconds add 1 to the value of the address in register 8. The error signal from comparison circuit 10 is output to the processor at a level of 28.. In the event of a failure or mismatch of two timers 11 and 12, the signal from comparison circuit 13 nulls timers II and 12 and issues a request for regeneration via bus 26 to block 3. The error signal from comparison circuit 13 passes bus 28-2 to the processor. The simultaneous start of time slots on start-up from the processor and regeneration is excluded by the shift of synchronization pulses. The counter 7, the timers 11 and 12, and the block 3 are zeroed by the signal on the bus 25 of. processor. Block 3 works as follows (Fig. 4). In the initial state, the outputs of the register 40, triggers 41, .43 and 45 are located at logic level 1., and the outputs of the triggers 42, 44, 46 and 47 logical O. If there is a START signal on bus 15 and no regeneration signal is received bus 26 and the regeneration cycle) in register 40, a timing diagram is triggered (a logic level O signal appears at the first output of register 40). At the same time, from the output of trigger 4, a logic level O signal with a duration of 2 cycles is issued, which means that the memory has been started up from the processor. At the output of the AND-NOT 53 element, a signal is generated, which is fed to the inputs of the AND-OR-HE 56-63 element circuits. The output level signal of one logic one of them triggers memory 1. The output number of the output output is determined by the value of the three most significant bits output via the bus 14. A slug on bus 17 simultaneously with the signal on liiKHe 16 is output from the trigger 41 output. ADDRESS information from the processor is connected by a logic level signal from the output of the NE-55 element via bus 29. Through switch 5 to memory 1. A write signal on bus 22 is not output if the address parity error is detected by nodes 75 and 76 (FIG. 6) and (or) information. According to the time diagram of memory 1 operation, this signal appears with a delay T | 2 relative to the leading edge of the signal CE (Fig. 3). The end of work signal on memory 1 is output with a delay from trigger 46. During the regeneration operation, the signal from logic bus level 26 trips 42 is set to one, so that if the memory is not occupied, a time regeneration diagram is started in the block 3. When a logic level signal appears at the second output of the register 40 and logical O at the output of the NOT 50 element, the output of the trigger 41 sets the logic level (FIG. 4). At the output of the AND-NE element 53, a strobe of the required duration appears, which is supplied on the elements AND-OR-NOT 56 -63 simultaneously with the signal from the trigger 41. From block 3 (Fig. 4) eight signals are inserted via bus 16, which leads to regeneration of the selected memory line 1. A zero signal is output from the output of the IS-NOT element 55, which connects via bus 29 the output of the counter 7 through the switch 5 to the memory input 1. In this case, the signal on the bus 17 has a logic level. In the circuit of adder 69 (FIG. 6), a code of 3 out of 7 is used to correct single errors and detect errors of greater multiplicity. A single error in node 74 (box 6) is generated if at least one bit of a 7-bit correction code (for each half-word) is not equal to O (when reading). In the case of a single error, the three signal level logic bus 97 (Fig. 7) is sent to the elements HE 79-85. Then the signal level of logical 1 s. Of the output of the NAND 88 element is gated by the signal from the output of the trigger 95 and the signal of the corrected error from the output of the NAND 86 element enters the bus ZZu. The signaling error-correcting error is calculated at node 75, and the bits of the correction code on bus 97 arrive at elements 89, -94 of addition (Fig. 7). If at the output of the element HE 87 there appears a signal of the level of logical i and at least one of the correction code is not equal to O, i.e. from the output of the element IS-NOT 88, a logic level signal is output, then the trigger signal 95 from the output of circuit 96 causes an uncorrectable error signal to bus 33. In the decoder 73 (FIG. 7) containing the control unit 74 being correctable and the uncorrectable error block 75 for one half-words, control nodes for the second half-word will be similar. The address information in convolution circuit 77 (FIG. 6) is monitored modulo two, both by writing and by reading from memory 1. Recorded information is monitored. S convolution circuit 78. The shaper 6 (Fig. 5) works as follows. If information is recorded and the parity errors are not detected by circuits 77 and 78 supervising ki, the bus level signals are transmitted over buses 19, 20, 20 and 98. 21 is a logic level signal (FIG. 3) and a signal is output to the bus from the NAND 65 element (FIG. 5). If the parity of the address and / or information occurs, then a signal is generated on bus 20 and (or) 20 the logical level, which blocks the recording signal on the bus 22 and at the output of the element IS-NE 6, the level of the logical i is maintained (Fig. 2). The sync signal on bus 984 is provided to form the necessary signal duration on bus 22. Thus, the proposed device allows to effectively implement protection and formations in a dynamic integral memory accumulator from distortion in the event of an error in the input information, address or operation code. In addition, the speed of the device is improved compared with the prototype, since there is no loss of time to generate the control bits. Input control and the formation of control codes of the accumulator (i.e., the conversion of data formats in case of their differences in the processor and the accumulator) occurs during the operation of the input amplifiers and decoders of the accumulator elements, i.e. a temporary pause is used (between the start-up of the memory element (CE) and the issuance of the write operation code, which is inherent in the dynamic memory elements and is 0.2-0.25 of the element operation cycle. (Fig. 3). The proposed device increases the speed of the processor Since the device sends the CE signal to the drive immediately after receiving the START signal from the processor, without waiting for the result of the input control performed by the information control circuit.

Address

FIG. five

22

6s

Fsh five

J4

Claims (3)

1. DEVICE FOR CONNECTING THE PROCESSOR. WITH MEMORY, containing a control unit and an information control unit, the first inputs of which are connected to the input of the device address, the second, third inputs and the first, second and third outputs of the control unit are connected respectively to the reset and start inputs devices and control outputs, samples and the end of the device, and the fourth output with the second input of the information control unit, the third and fourth inputs connected respectively to the first and second information inputs of the device, and the first, w eye, third and quarter ”* outputs - respectively, with the outputs of the address and information control signal, error correction signal, information output and the device correction code output, characterized in that, in order to increase the reliability of information transmission and speed, a regeneration unit is introduced into it, an address switch and a shaper of the recording signal, the first, second inputs and the first output of the regeneration unit respectively connected to the second input, fifth output and fourth input of the control unit, and the second, third and the fourth outputs, respectively, to the first input of the address switch and the outputs of the address error signals and the device regeneration period errors, “the first input of the recording signal shaper is connected to the sixth output of the control unit and the fifth input of the information control unit, the second and third inputs, respectively, with signal input ¹ 'operation code' of the device and the sixth input and the first output of the information control unit, and the output with the output of the device recording signal, the second and third inputs of the address switch are connected respectively to the seventh the control unit’s progress and the device’s address input, and the output with the device’s address output, and the regeneration unit contains two comparison circuits, two timers, a convolution unit, a regeneration address counter and a register, moreover, “the output of the first comparison circuit is connected to the third output of the block and the first input of the register, the first input to the output of the register and the first input of the counter of the regeneration address, the output of which is connected to the second input of the register, the second output of the block and through the convolution node with the second input of the first comparison circuit, the output of the second comparison circuit The unit is connected to the fourth output of the unit and to the first inputs of the timers, the second inputs of which are connected to the first input of the unit, the output of the first timer is connected to the first input of the second comparison circuit, the second input connected to the first output of the second timer, the second output of which and the second and third inputs the regeneration address counter is connected respectively to the first output and the first and second inputs of the unit, and the control unit contains three AND-OR-NOT elements, two elements OR-NOT., shift register, processor trigger, regeneration trigger, five delay elements, four NOT elements, four AND-NOT elements and a group of AND-OR-NOT elements, the first inputs of the first and second elements AND-OR-NOT connected to the third input of the block, and the outputs' respectively to the information inputs of the shift register and the trigger of the processor, the first input of the third AND-ORINE element is connected to the fourth input of the block, and the output is to the information input of the regeneration trigger, reset input the shift register is connected to the second input of the block, and the first output with the first inputs of the first and second NAND elements and through the first delay element with the fourth output of the block, the second input of the second NAND element and the first input of the first OR-HE element, the output of the first eleme that AND is NOT connected through the first element NOT to the second and third inputs of the second AND-OR-NOT element, the first output of the shift register is connected to the first input of the second OR-HE element, the output of the regeneration trigger is Connected via the second element NOT to the second inputs of the third and first AND-OR-NOT elements, the third input of which is connected through the third element NOT to the processor trigger output, the second block output, the second outputs of the first and second OR-HE elements and the first inputs of the AND-OR-NOT elements of the group and the third and fourth AND elements NOT whose outputs are the fifth and seventh outputs of the block, the second shift register output is connected to the second input of the first AND-NOT element, the fourth and fifth inputs of the first AND-OR-NOT element and through the fourth element NOT and the second delay element to the second input of the third AND-NOT element and the third input of the third AND-OR-ΗΕι element, the fourth input connected through the third delay element to the output of the processor trigger, the regeneration trigger output is connected to the second input of the fourth AND-NOT element and the fourth input of the second AND-OR-NOT element the first and second OR-HE elements are connected respectively through the fourth and fifth delay elements to the third and sixth outputs of the block, the second and third inputs of the AND-OR-NOT elements of the group are connected to the output of the second AND-NOT element, the fourth inputs form the first input of the block, and the outputs are his first exit. 2, The device according to π. 1, wherein the information control unit comprises an information register, a control code register, an information switch, a control code adder, two bitwise adders, a corrected digit number decoder, an error type decoder and a parity node, the output of the parity check node is the first output of the block, and the first, second and third inputs are, respectively, the first, fifth and third inputs of the block, the first and second inputs of the register of control codes and information register are connected respectively to the fourth and the second inputs of the block, and the outputs, respectively, with the first inputs of the first and second bitwise adders, the first, second and third inputs of the information switch are connected respectively to the output of the information register and the third and sixth inputs of the block, and the output to the adder of the control code, the first output of which connected to the second input of the second bit adder, and the second output to the fourth output of the block and the second input of the first bit adder, the output of which is connected to the first input of the error type decoder, and through the fractor of the corrected discharge number with the third input of the second bit adder, the output of which is the third output of the block, the second input of the error type decoder is the second input of the block, and the output is its second output. 3. The device according to claim 1, wherein the recording signal conditioner comprises an OR-HE element and an AND-NOT element, the inputs of the OR-HE element being the first and third inputs of the former, respectively, and the output is connected to the first input of the element that AND NOT, the second input and output of which are, respectively, the second input and output of the shaper.