SU1536445A1 - Device with correlation of flaws and errors - Google Patents

Abstract

The invention relates to computing and can be used in random access memory devices to increase the reliability of their operation. The purpose of the invention is to increase speed. The device contains information inputs-outputs 1, input register 2, inverter block 5, additional key block 7, first switch 9, encoding-decoding block 10, module 11 adders modulo two, second switch 13, encoder 15, fixed memory block 16 TI, output register 19, address inputs-outputs 23 of the device, control inputs 24-35, outputs single 36 and multi-bit 37 errors. 3 il.

Description

coding-decoding, block 11 modulo-two adders, second switch 13, encoder 15, permanent memory block 16, output register

19, the address inputs-outputs 23 of the device, the control inputs 24-35, the outputs of a single 36 and multi-bit 37 errors. 3 ill., 1 tab.

The invention relates to computing technology and can be used in random access memory devices to increase the reliability of their operation.

The purpose of the invention is to increase the impact.

FIG. 1 shows a block diagram of a memory device with the correction of defects and errors; in fig. 2 - encoder structured diagram; in fig. 3 - block diagram of the first switch.

The device (Fig. 1) contains information inputs-outputs 1, input register 2, outputs of block 3 of keys, inputs 4 of the second group of block 5 of inverters, inputs 6 of the first group of block of inverters, additional block 7 of keys, outputs 8 of the second group of additional block of keys, first switch 9, block 10 encoding-decoding, block 11 modulo-two adders, outputs 12 of the first group of an additional key block, second switch 13, inputs-outputs 14 of the second group of a coding block-decoding, encoder 15, block 16 memory, inputs 17 of the first group modulo two, inputs 18 of the first group of the first switch, output register 19, fourth inputs, outputs 20 of the first switch, inputs 21 of the RAM block 22, device address inputs 23, the first synchronization input 24, the first mode setting input 25, the second mode setting input 26, group mode setting inputs 27, third mode setting input 28, second synchronization input 29 third synchronization input 30, fourth mode setting input 31, fourth synchronization input 32, fifth mode setting input 33, access input 34, read write entry 35 , outputs single 36 and multi-bit 37 errors.

The encoder (Fig. 2) contains registers 38 and 39 and the second permanent memory unit 40.

five

five

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0 5 0 0 5

five

The first switch (Fig. 3) contains a block of 41 keys, a block of 42 keys and. unit 43 inverters.

The device works as follows.

During the first cycle of recording information on the bus 23, an address code is set, and on the information bus 1 an information word (for example, sixteen bits) is set to be written.

By a signal on bus 24, this word is written to input register 2. In the absence of a signal on bus 25, the inverter unit 5 does not invert the information received at inputs 4 and 6. Then the signal comes through bus 26, opens Olok 7 keys and appears at outputs 8 input information word (non-inverted), and outputs 12 - zeros (in this example, four bits).

A combination of signals corresponding to the input information coding mode appears on the control inputs 27, and the check bits of the corresponding Hamming code (six bits in the example considered) appear on the outputs 14 of the control bits of block 10.

In the absence of a signal on the bus 28, the first switch 9 connects the inputs-outputs with the inputs-outputs 20.

Thus, the input information non-inverted word (16 bits), address information bits - zero, (four bits) and Hamming test bits (six bits) are received through the switch .9 to the inputs-outputs 21 of the RAM 22 and, under the influence of the recording signals, the bus 34 is written to it at address 23.

Then the first cycle of reading information occurs.

The signal from the bus 26 is removed and the key block 7 is turned off. On bus 35, a readout signal and information from outputs 21 of accumulator 22 appear through switch 9 to the inputs of decoding unit 10. At entrances 27

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A combination of signals appears, recording the read information in decoding unit 10.

Then, the signal 35 is turned off and a signal appears on the bus 28, at which the inputs-outputs of the switch 9 are disconnected and the inputs 18 and the inputs-outputs 20 are connected. At the inputs 27 there appear signals executing the output. corrected information; at outputs 14, an error syndrome, which, under the influence of a signal via bus 29, is recorded in an encoder.

At the outputs 36 and 37 errors, the corresponding signals appear. If there are no errors, the recording of information in the storage device ends. If error signals appear at the outputs 36 or 37, the device proceeds to the second cycle of writing and reading information. In this case, an inversion signal appears on bus 25, a switch on the key block on bus 26, a coding signal on bus 27, a switch signal is received from bus 28. The inverted information from outputs 8 goes to block 10 and through switch 9 to the inputs of accumulator 22, from outputs 12 the single word also goes to block 10 and to inputs of accumulator 22, and from outputs 14 the corresponding check bits also go to inputs of accumulator. The bus 34 receives the recording signal and the inverted information word, together with the single information part and the corresponding check bits, is recorded in the operational memory 22. The signals on the buses 34, 25, 26 and 27 end.

The device proceeds to the second read cycle. A read signal appears on bus 35 and information from accumulator 22 enters the inputs of block 10 and under the influence of signals on buses 27 is written to block 10, then a signal appears on bus 28 that switches switch 9, inputs 27 receive signals making the output of the corrected information from block 10. At outputs 14, an error syndrome appears, which enters the inputs of the encoder 15 and is written to it under the influence of a recording signal via bus 30. At the outputs of error, the corresponding signals appear to the buses

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30 and 37. If there are no error signals, the information is written to the memory device.

If bus 37 does not have a multi-bit error signal, if a single error signal is present on bus 36 and if only a single error is detected in the first read cycle, the device proceeds to the third write-read cycle (if multi-bit errors were detected in the first write-read cycle , and in the second cycle - one-bit or multi-15-bit ones, it means that the quantity at this address exceeds the correction ability of the device - two defects).

Tire Signals Terminate 27

20 and 30.

In the third recording of information, a block of 7 keys is opened by a signal on bus 25, a combination of coding signals and information in the forward code is set up on buses 27 to the inputs of coding block 10 and the inputs of modulo-two block 11, together with zero address information signals and the corresponding 30 control bits from the outputs 14. The encoder 15, using the two syndromes of single errors of the direct and inverse information words recorded in it, generates the address code of the matching word, which comes in a second th switch 13 to the address inputs of the DC accumulator 16, Matching word (in this example dvadtsatishestirazr The battery) is supplied to

40 OTHER INPUTS 17 of block I1 modulo-two adders, where it is summed with the information word. From the output of block 11 adders information is fed to the inputs 18 of the first switch 9 and

45 after the arrival of the switching signal, the bus 28 enters the inputs / outputs 21 of the accumulator 22. The bus 34 receives the recording signal and the summed information is recorded in the accumulator 22.

5o Together with the termination of the signals on the buses 34, 28 and 26, the cycle of recording information in the memory device ends.

If at this address in the operational storage 22 there were no more

55

two defects, it is guaranteed that information is recorded in a form consistent with the defects in no more than three read write cycles.

When reading ithfmdtsii with tires 23 in the drive 22 receives the address code.

Bus 35 receives a read signal and information from output 21 through the first switch 9 enters the inputs of block 10 and is written to it when the corresponding signals arrive through bus 2.

Then, the inputs 27 receive the signals for outputting the corrected information (one malfunction that occurred during the storage of information in the drive is corrected). The information is fed to the inputs of the modulo-two adder unit 11, and the signals of the address information bits are received through the second switch 13 when the signal arrives on the bus 31 to the address inputs of the fixed storage device 16. The corresponding matching word from the fixed storage device 16 (the same as used when recording information in the operational drive) enters the inputs of the 17 block modulo two adders,

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A distinctive feature of this Hamming matrix is the oddness of all columns, which makes it possible to determine two — four-fold errors and errors of greater multiplicity.

The matching words are written in the form of a matrix C, which has the following properties: all the rows of the matrix are code words of the linear code generated by the encoding-decoding unit 10 in accordance with the Hamming matrix 44.

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five

the output of which appears correct-. The information word, which is written to the output register 19 under the influence of the signal on the bus 32.

Then, the signal on bus 33 turns on a block of 3 keys and the read information is fed to information buses 1.

Single direct word error syndrome is recorded in register 38, and single inverse word error syndrome is recorded in register 39. The codes of the two syndromes determine the address of the permanent accumulator 40, where the address of the matching word of the matrix C (see table), stored in the permanent accumulator 16, is written.

The table shows, for example, the generator matrix of a modified Hamming code for a twenty-bit word, a sixteen-bit information word 45 with a four-bit address information part. Six test digits 47 are used to encode this twenty-bit word.

47

The address codes of all matching words are different (the first four bits of each matching word), any two columns of the matrix C must contain all combinations of 1 and 0 (00, 01, 10, 11), one row of the matrix C must be single.

The C 48 matrix is similar, such that if there are two any defects in the storage device 22, there will be a code word in any address in it, which, when added to the information word, hassles;

The children are stored at this address without any errors.

Example. Suppose that the 16-bit word 11) 011000110001I is fed to the inputs 1 for writing. At outputs 12, address 0000 will be added and, after coding in block 10, coding at outputs 14, the control bits 1111JO are in cc.

3 drive 22 will write twenty six-sixth word x. 49. If, when reading the same word from accumulator 22, there are no errors in it (50), then when decoding in block 10, the 15- information part is written in rum 51 is zero (all bits are output register 19).

57 error decoder does not detect and the syndrome is zero.

When reading a word in which 5 there was one malfunction, for example, in the second bit, in 58 when decoding with blue it is 111110, which indicates an error in the second bit. After correction, the information in the second category will be restored (59). The first four bits of the word 1100 are the address of the row of the C 55 matrix, which is read from the persistent accumulator 16, added to the word 59 and

ten

Roma are zero). If there are defects in this cell of accumulator 22, for example, in the sixth position (marked with an asterisk), O is read instead of 1 instead of 1, then when reading and decoding the word y. (error syndrome 52), at output 14 of block 10, upon decoding, syndrome 110100 appears, which is written into the encoder 15. The writing process continues. The input word is inverted by the inverter unit 5 as word x; 53 11P 0001001P 001I10000000 is written to drive 22.

If, after reading and decoding the inverted word, a single error is detected in 54, for example, in the thirteenth bit (zero is read instead of a one), then the syndrome will be 011010.

The codes of the syndromes of the read straight 52 and inverse 54 words define the row of the matrix C 48 (the row must have zero in the sixth column and zero in the thirteenth column of the matrix C 48).

This selection of combinations of syndromes and rows of matrix C is made in advance when programming persistent accumulator 40 of encoder 15. In this case, the desired row of matrix C is the word 55 1100111000000000110110000J, in which in the sixth digit will be one, and in the thirteenth bit - zero.

After adding the row of the matrix C; and the source word x; in the block adders 1 1 modulo two, we get the word 56 1100000011000110111001111, which will be written to the drive 22 without errors.

When reading the agreed uto without any occurrence during storage

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glitches;

ten

15, the information part is written to output register 19.

57 error decoder does not detect and the syndrome is zero.

When reading a word in which 5 there was one malfunction, for example, in the second bit, 58 when decoding, the syndrome is 111110, which indicates an error in the second bit. After correction, the information in the second category will be restored (59). The first four bits of the word 1100 are the address of the row of the C 55 matrix, which is read from the persistent accumulator 16, added to the word 59, and

ten

This word corresponds to the recorded word 49. Thus, the proposed device provides for the correction of double defects of the operational accumulator 22 and one failure that occurs during the storage of information.

the invention

Formulas

A memory device with correction of defects and errors containing a block of RAM, whose address inputs are the corresponding inputs of the device, the input register, whose information inputs are connected to the outputs of the key block and are information inputs-outputs of the device, the information inputs of the key block are connected to the outputs the output register, a block of permanent memory, the outputs of which are connected to the inputs of the first group of the block of modulo-two adders, the outputs of which are connected to information

the inputs of the output register, the coding-decoding unit, the control inputs of which are a group of mode setting inputs, the synchronization input of the input register is the first

the synchronization input of the device, the synchronization input of the output register is the fourth synchronization input of the device, the control input of the key block is the fifth input of the register setting

device press, ram storage block input is the corresponding input of the device, the write-read input of the ram memory is the corresponding input of the device, characterized in that, in order to increase the speed of the device, an inverter block, an additional key block, first and second coder

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the switches, the outputs of the input register are connected to the information inputs of the first group of inverter unit, the information inputs of the second group of which are the inputs for setting the initial operation mode of the device, the direct outputs of the inverter block are connected to the information inputs of the first group of the additional block of the key, the inputs of the second group of which are connected to inverted outputs of the inverter unit, the first outputs of the additional key block are connected to the information inputs of the first group of the second switch, information and the inputs-outputs of the first group of the first switch, the inputs of the coding-decoding block group, the inputs of the fourth group of the modulo-two adders block, the outputs of the second group of the additional key block are connected to the information inputs-outputs of the coding-decoding block, information inputs-outputs of the third group of the first switch and the inputs of the third group of modulo-two adders, the control inputs / outputs of the coding-decoding unit are connected to the information inputs of the encoder, the information

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"10 53644512

by the inputs of the second group of the first switch and the inputs of the second group of the modulo two adders, the outputs of the modulo adders block two are connected to the information inputs of the first switch group, the outputs of the second switch are connected to the address inputs of the permanent memory unit, the outputs of the encoder are connected to the information inputs of the second groups of the second switch, information inputs-outputs of the fourth group of the first switch are connected to information inputs-outputs of the RAM block, control input of the block Inverters are the first input of the device mode setting, the control input of the additional key block is the second input of the device mode setting, the control input of the first switch is the first input of the device mode setting, the first and second encoder synchronization inputs 25 are the second and third synchronization inputs, respectively the devices, the control inputs of the key block and the second switch are the third and fourth inputs of the mode assignment, respectively.

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devices.

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Claims (1)

Claim A memory device with correction of defects and errors, containing a random access memory block whose address inputs are the corresponding inputs of the device, an input register, the information inputs of which are connected to the outputs of the key block and are the information inputs and outputs of the device, the information inputs of the key block are connected to the outputs of the output register , a read-only memory block, the outputs of which are connected to the inputs of the first group of the adder block modulo two, whose outputs are connected to the information inputs in the input register, the encoding-decoding unit, the control inputs of which are a group of mode setting inputs, the input register synchronization input is the first device synchronization input, the output register synchronization input is the fourth device synchronization input, the key block control input is the fifth device mode task input, and the operational block input memory is the corresponding input of the device, the write-read input of the RAM block is the corresponding input of the oystva, characterized in that, in order to improve device performance, it introduced a block of inverters, additional unit keys, encoder, first and second 1 1 switches, the outputs of the input register are connected to the information inputs of the first group of the inverter block, the information inputs of the second group of which are inputs of the initial operation mode of the device, the direct outputs of the inverter block are connected to the information inputs of the first group of the additional key block, the inputs of the second group of which connected to the inverted outputs of the block of inverters, the first outputs of the additional block of keys are connected to the information inputs of the first group of the second switch, information and the inputs and outputs of the first group of the first switch, the inputs of the group of the coding-decoding block, the inputs of the fourth group of the block of adders modulo two, the outputs of the second group of the additional block of keys are connected to the information inputs and outputs of the coding-decoding block, the information inputs and outputs of the third group of the first switch and the inputs the third group of the adder block modulo two, the control inputs and outputs of the decoding coding block are connected to the information inputs of the encoder, information 1536445 and the inputs of the second group of the first switch and the inputs of the second group of the adder block are modulo two, the outputs of the adder block modulo two are connected to the information inputs of the group of the first switch, the outputs of the second switch are connected to the address inputs of the read-only memory, the outputs of the encoder are connected to the information inputs of the second group of the second switch, the information inputs and outputs of the fourth group of the first switch are connected to the information inputs and outputs of the RAM block, the control input of the inv block ertor is the first input of setting the device mode, the control input of the additional block of the key is the second input of setting mode of the device, the control input of the first switch is the first input of setting mode of the device, the first and second synchronization inputs 25 of the encoder are the second and third inputs of synchronization of the device, the control inputs of the key block and the second switch are the third and 30 fourth inputs of setting the device mode, respectively. (rig. I figz