SU1297120A1 - Storage with error correction - Google Patents

Abstract

The invention relates to computing and can be used to create memory systems based on an LSI memory device with a dictionary. by conversion. The purpose of the invention is to increase the reliability of the device. The device contains a drive 1, an address unit 4, a switch 5, a number register 7, a comparison block 8, a syndrome shaper 10, a correction block 14, an AND 15 element, an OR 17 element, a And 19 element group, an unrecoverable error detection unit 20, adders 23 through module two, block 26 information output. The reliability of the device is increased due to the fact that it corrects errors in several LSIs that are part of accumulator 1, provided that the errors do not belong to the same name (in order of arrangement) symbols recorded in different LSIs when storing one word. 1 hp f-ly, 3 ill. 1 (L with to with N3

Description

The invention relates to computing and can be used to create memory systems based on an LSI memory device with a dictionary of circulation.

The purpose of the invention is to increase the reliability of the device.

FIG. i shows the block diagram of the proposed device; in fig. 2 - functional block diagram of the detection of unrecoverable errors; in fig. 3 - connection of the inputs of the group of elements I with the outputs of the comparison unit and the former of the syndrome.

The device (Fig. 1) contains a drive 1, the address .2 and informational 3 inputs of which are connected respectively to the outputs of the address unit 4 and switch 5. The output 6 of the storage device is connected to the inputs of the register number 7 and one of the inputs of the comparison unit 8, the other inputs of which are connected to direct outputs 9 of register 7, also connected to the inlets of the former 10 of the syndrome. The inverse outputs of the register 7 are connected respectively to the inputs 11 of the switch 5, the inputs 12 and 13 of which are connected respectively to the information input of the device and to the output of the coding unit 14. The device also contains an element 15, the output 16 of which is connected to the control inputs of the switch 5 and register 7, an element OR 17, the inputs 18 of which are connected to the outputs of the driver 10 and one of the inputs of a group of elements 19, the uncorrected error detection unit 20 with the inputs 21 and an output 22, an adder 23 modulo two, one of the inputs of which are connected to one of the direct outputs 9 of the Receiver 7, the others to the outputs 24 of the elements And 19, and the outputs 25 of the adders 23 to the inputs of the information output block 26 27. Inputs 28 of address block 4 are address in One device, the control input 29 of the device is connected to the control inputs of the accumulator 1 and one of the inputs of the element 15.

Block 20 (Fig. 2) contains a group of elements And 30, the first group of elements OR 31, the second group OR 32, the element OR 33, adders 34 modulo two.

The device works as follows. On the direct outputs 9 register 7 null characters. In the mode of recording information to the input 12 of the switch 5, the input of block 14 receives “k and information symbols that need to be written to drive 1 at the address specified by block 4. Coding block 14 generates“ b control characters s. The code word thus formed of the length of the k- | -b bits according to the recording signal at the input 29 of the device is recorded in the drive 1.

Example. Suppose that you need to write a 16-bit word into the drive: 1000 1100 0010

1111 (k 16). The drive is built on the basis of 4-bit E) IP memory (L 4), i.e. in relation to one LSI, information can be simultaneously recorded in 4 elements (or read). The coding unit generates 4 control symbols: a 1000-bit and a 20-bit code word is written into accumulator 1

At this point, the recording cycle is over.

In the read mode (set by the opposite write mode by a logical signal at input 29), the read information (20 bits) is written to register 7. Shaper 10 generates the "L" new test symbols (syndrome). If in the word 1 read from the accumulator there is no error, then all the bits of the syndrome are zero and the syndrome is not zero - otherwise. If there are no errors in the read word, then the outputs of blocks 8 and 20 and elements 19 And there will be zero signals. Information symbols from outputs 9 of register 7 pass through

adders 23 and further in block 26 unchanged. Block 26 (at a certain point in time determined by the processor) provides information to the destination. If there are errors in the read word in all rows of the same LSI or in opposite digits of different LSIs (in both cases, the total number of errors is not greater than b), then at the output of the OR 7 cell, a single signal appears, and 15 sets the control input of the switch 5 to a signal that sets the inputs 3 of the accumulator 1 to an inverse with respect to the read code word, which is written into the same cells of the accumulator. Then a check reading of the inverse code word is performed, which

in block 8, it is compared with the previously read (direct codeword). The state of register 7 is unchanged. The outputs 21 of block 8, which correspond to the failed bits, will have single signals, since even when writing to the failed cell of an inverse signal, its logical state does not change. If the opposite bits in different LSIs are faulty, then the output 22 of block 20 will be a zero signal, a single signal will be in case of failure of at least two (for example, second or fourth) cells of the same name. In the latter case, at the output 22 of block 20, the signal “Failed error. If the output is 22- “O, then the output of the And 19 elements corresponding to the failed bits, if ly, are single signals, which in the corresponding adders 23 will invert the erroneous bits from the number of information that arrive at the inputs of the adders 23 from the outputs 9 of the register 7. If among the failed will appear the bits belonging to

control characters, this does not affect the reliability of the information characters. Suppose that the accumulator bits correspond to the first, second, and seventh

The symbols of the code word are defective and are in the state "1, bits 16 and 17 (control) are in the state O i. The read word will be as follows: 1100 1110 0010 1110 0001 (the failed bits are underlined). For the read information symbols in the former 10, the control characters 1110 and the syndrome 1110 - | - 0001 1111 will be calculated (the bits of the same name are added, the summation leads modulo two). At the outputs of the comparison unit 8 there will be the word 0100 0010 0000 0001 1000 (after writing the inverse code word 1 into the drive and reading it). At the output of the 22 block 20 "O. The following binary symbols arrive at the inputs of the AND 19 elements, respectively: 1111 and 0100 0010 0000 0001, at the outputs 25 of the adders 23 modulo two - the original information word without errors 1000 1100 0010 1111.

Claims (2)

1. An error-correcting memory device containing an address block, an accumulator, a switch, a number register, a coding block, a comparison block, a syndrome former, an AND element, an AND group, an OR element, two modulators and an information output block, and the address inputs The accumulator is connected to the outputs of the address block, the inputs of which are the address input of the device, the information inputs of the accumulator are connected to the outputs of the switch, one of the information inputs of which and the inputs of the coding block are combined and are data input devices, other data inputs of the switch are connected respectively to the outputs of block encoding and the inverse outputs of the register, accumulator outputs are connected to data inputs of the register and one of the inputs of the comparison unit, the other the inputs of which and the inputs of the syndrome generator are connected to the direct outputs of the number register, one of the modulo adders two inputs are connected to the direct outputs of the number register, the other inputs - with the outputs of the AND group elements, one of the inputs of which and the inputs of the OR element are connected to the outputs of the imager syndrome, the output of the element OR is connected to one of the inputs of the element AND, the other input which, as well as the control input of the accumulator, are combined and are the control input of the device, the output of the AND element is connected to the control inputs of the number register and the switch, the outputs of modulo-two adders are connected to the information inputs of the information output unit, the outputs of which are the information output of the device , characterized in that, in order to increase the reliability of the device, an unrecoverable error detection block is inserted into it, the inputs of which are connected to the outputs of the comparison block, and the output is connected to the control input information output from the block and is a control output of the apparatus, other inputs of the group of AND gates are connected to one from the outputs of the comparison unit. 2. A device according to claim 1, characterized in that the unrecoverable error detection unit comprises groups of elements AND, first and second groups of elements OR, modulo-two adders and element OR, whips; inputs AND elements are the inputs of the block, and the outputs of the AND elements of each group are connected to the inputs of the corresponding OR elements of the first group, the outputs of which are connected to the first inputs of the corresponding modulators are two, the second inputs of which are connected to the outputs of the corresponding elements OR of the second group of inputs are connected to the inputs block outputs modulo two are connected to the inputs of the OR element, the output of which is the output of the block. Compiled by V. Rudakov Editor N. Gorvattehred I. VeresKorrektor A. Znmokosov Order 595/55 Circulation 590 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 1 13035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 GI fig.Z