SU1510007A1 - Device for monitoring errors of digital magnetic recording channel - Google Patents

Abstract

The invention relates to measuring storage media and can be used to monitor the errors of channel 1 of a digital magnetic recording-reproducing self-synchronizing signals. The aim of the invention is to improve the accuracy of the control. The device contains a generator of 2 clock pulses, the first 3, second 4 and third 5 shift registers, block 6 of the control input error, consisting of adder 25 modulo two, trigger 26, button 27, trigger 28, trigger 29, element 30, counter 31 and inverter 32, decoder 7, adder 8 modulo 2, gate element 9, counter 10 errors, unit 11 for setting a digital signal, first 12, second 13 and third 14 with clock pulses, electronic switch 15, button 16, first 17 , the second 18, the third 19, the fourth 20 and the fifth 21 triggers, the first 22 and second 23 elements And indicator 24 of control signal generating mode. The goal is achieved by using a test signal in the form of a periodic sequence consisting of two structures: fixed code combinations — words whose structure is the same and most difficult for a given channel, and pauses between words to which, i.e. to the prolonged absence of digital signal drops, the channel clock sync recovery system is critical. Errors are allocated by element-wise modulo-two comparison on the adder 8 of the reproduced signal with the reference, reference signal generated synchronously with the reproduced elements: register 5, when its output is closed with the information input by the switch 15, the decoder 7, the triggers 18 and 21, and the counter 14. Dedicated errors are overwritten into trigger 20, gated on element 9 and counted by counter 10. Button 16 turns on the control signal generation mode, in which, besides registers 4, 5, decoder 7, adder 8, participate, triggers 20, 18, 21 and counter 14, another trigger 17, elements 22, 23, counter 13 and trigger 19. Block 6 provides a possibility of promptly introducing a known number of errors into the test signal, the selection and exact counting of which by counter 10 indicates good health and accuracy of the device. 1 il.

Description

ate

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of the structure consisting of two structures: of fixed code combinations — words whose structure is the same and most difficult for a given channel, and pauses between words to which, i.e. To the long absence of digital signal drops, the system of restoring the clock sync signal of the channel playback is critical. Opscams are selected by element-wise modulo-two comparison on the adder 8 of the reproduced signal with the control, reference signal generated synchronously with the reproduced elements — the register 5, when its output is closed with the information input by the switch 15, the decoder 7, the triggers

18 and 21 and counter 14. The errors selected are rewritten into trigger 20, gated on element 9 and counted by counter 10. Button 16 turns on the control signal generation mode, in which, apart from registers 4, 5, decoder 7, adder 8, triggers 20, 18, 21 and counter 14, another trigger 17, elements AND 22, 23, counter 13 and trigger 19. Block 6 provides the possibility of promptly introducing a known number of errors into the test signal, the measurement and accurate counting of which by counter 10 indicates the health and accuracy of operation mustache the trials. 1 il.

The invention relates to the measurement of storage media, namely, devices for monitoring the errors of a digital magnetic recording channel. The purpose of the invention is to improve the control accuracy by taking into account the influence of the structure of the measuring signal on the synchronization accuracy of the channel 1FERFECT magnetic recording.

The drawing shows a functional diagram of the device for monitoring errors of a channel of a digital magnetic recording.

A device for monitoring errors of digital magnetic recording-reproduction channel 1 contains a generator 2 clock pulses, the first 3, second 4 and third 5 shift registers, an error input block 6, a decoder 7, a calculator 8, a strobe element 9, a counter 10 errors, digital signal setpoint generator 11, first 12, second 13 and third 14 clock counters, multiplexer 15, switch 16, first 17, second 18, third 19, fourth 20 and five five triggers and first 22 and second 23 elements I. The device can also contain an indicator 24 about signal.

The error input block 6 contains the sum of op 25 modulo two, D-flip-flop 26, button 27, flip-flop 28, flip-flop

29, the element And 30, the counter 31 clocks and inverter 32.

The output of the generator 2 clock pulses is connected to the clock input of the shift register 3, with the clock input of the block 6 of the control input of errors and with the inverse counter input of the counter 12 clock pulses, the output of the higher bit of which is connected to the control input of the parallel input of the shift register 3. The outputs of the setting device 11 of the digital signal are connected to the inputs of the bits of the shift register 3, the output of which is connected to the information input of the control error input block 6, the output of which is connected to the information input of channel 1 of the digital magnetic recording. The information output of channel 1 is connected to the first signal input of the electronic switch 15 and to the information input of the shift register 4, the output of which is connected to the first input of the adder 8, the output of which is connected to the first information input of the trigger 20. The output of the multiplexer 13 is connected to the second input of the adder 8 and c the information input of the shift register 5, the output of the last bit is connected to the second signal input of the electronic switch 15. The output of the switch 16 is connected to the first clock input C of the trigger 17,

5 15

the direct output of which is connected to the first input of the element I 23, to the control input of the electronic switch 15 and to the input of the indicator 24.

The outputs of the bits of the register 5 shift is connected to the inputs of the decoder 7, the output of which is connected to the first information input of the D-flip-flop 18, the output of which is connected to the first clock input of the C-flip-flop 21 and to the first input of the element And 22, the output of which is connected to the second setting element the zero state by the trigger input 17. The trigger output 20 is connected to the zero-state counter input of 13 clocks, with the second zero-trigger input of the trigger 19 and the second signal input of the gate element 9, the output of which Wow connected to the counting input of the counter 10 errors. The output of the counter 13 of the tactile pulses is connected to the first clock: input of the C-flip-flop 19, the output of which is connected to the second input of the element I 22. The output of the counter of the 14-clock pulses is connected to the second reset input of the flashing 21, , is uniform with the inverse setting into the zero state by the input of the counter 14, with the blocking input (stop shift) of the shift register 5, and with the second input of the And 23 element, the output of which is connected to the blocking input of the shift register 4. The clock output of channel 1 of the digital magnetic recording is connected to the clock inputs of shift registers 4 and 5, with clock input of trigger 20, clock input of trigger 18, with the first strobe inverse of the strobe element 9 and counting inverse inputs of counters 13 and 14 clock pulses .

Connections within the control input block 6 errors the following Information input unit 6 is connected to the first. input. sump 25, the output of which is connected to the information input of the D-flip-flop 26, the output of which is connected to the code of block 6. The outputs of the button 27 are connected to the setup inputs of the flip-flop 28, one output of which is connected to the information input of the trigger 29, and the other (inverse) output - with the input to the zero state, the input of the counter is 31 cycles.

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Clock input block b is connected to the first input element I 30, to the clock input of the trigger 29 and to the input of the inverter 32, the output of which is connected to the clock input of the C flip-flop 26. Vkod element And 30 is connected to the counting input of the counter 31 clock cycles, the output which with: is connected to the zero-set-up input of the trigger 29, the output of which is connected to the second input of the adder 25 and to the second input of the element I 30.

Controlled channel 1 contains.

a recording current driver, recording and reproducing magnetic heads, a playback driver, and a clock synchronization unit.

At the input of channel 1 and, therefore, from its output, the information signal arrives in the usual potential form without returning to zero. The clock clock playback signal comes from the corresponding output of channel 1 in the form of a meander (duty cycle 2).

The device works as follows.

The test signal, formed by the device for monitoring the errors of channel 1, consists of a sequence of 16-bit code words, separated by pauses with a duration of 16 cycles, respectively. A pause is a sequence of ones or zeros, i.e. the periodic absence of digital signal drops, which tightens control of the channel's ability to recover the clock signal

from the playback signal.

The required structure of the word is set using the digital signal setting device 11. In this case, the code set of the word should contain the worst for

channel 1 is a code combination that is determined for a given channel experimentally or as a result of theoretical analysis.

Worst code combination for

This channel 1 magnetic recording-reproduction is such a combination that is transmitted by the channel with the greatest distortions of the informative parameter of the recorded signal.

First, we consider the work of the master part of the device.

Counter 12 switches over the decay of generator 2 clock pulses.

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The signal at the output of the counter 12 has v, the form of a meander (duty cycle 2) with a period of 32 cycles. During the high level of the output signal of the counter 12 with a duration of 16 clocks, a 1B-paired code word is written into register 3, which is formed at the inputs of 16 bits to register 3 by setting the digital signal 11. During this recording, i.e. during these 16 clocks, the information input (via block 6) of channel 1 is output from the last bit of register 3 constant level — low (logical O) or high (logical 1), depending on the value of the rightmost word bit. In this way, a pause is formed between adjacent words in the test signal.

During the second half period of the output signal of the counter 12, i.e. during the low level of the ov of this signal with a duration of 16 clock cycles, the 1b-bit word information is output from the register 3r. The information in register 3 is shifted along the front of the clock pulses of the generator 2, after the end of the word output, i.e. through the data of 16 clocks, a pause with a duration of 16 clocks, etc. is formed again at the output of the register 3.

The output test signal of the register 3 is supplied in the form of BVN through the block 6 of the control input of errors to the information input of the recording channel 1,

The control error input block 6 passes the test signal without changes and is used periodically to complete a comprehensive operational check of the device as a whole in conjunction with the monitored channel 1. The operator presses the button 27 of unit 6. The trigger 38 clears contact bounce of the button 27 and transmits its signals to the counter 31 and trigger 29. In this case, the lock is removed from the installation input from counter 31 and switches on the front of the next (after switching on trigger 28) clock pulse trigger 29. Output signal of trigger 2 tkryvaet AND gate 30 for the arrival of clock pulses to the counting input of the counter 31, and also receives

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to the second input of the adder 25, which at this ohm begins to invert the output signal of the register 3. As the clock pulses fall, the output signal of the adder 25 is copied to the trigger 26 and then goes to the information input of the channel 1. After 8 clocks, the output of the counter 31 is formed the signal that resets the trigger 29 to the initial state and keeps it in this state while the button 27 is pressed. Thus, the check number of errors in the test signal is entered in the form of a single inversion of 8 cycles of this signal- by recording it into channel 1. The measuring part of the device should detect these errors in the reproduced signal and count them exactly, which will indicate its operability and accuracy of error measurement.

The operation of the measuring part of the device.

Recording-reproduction errors of the test signal in the device are separated by element-by-element comparison on the adder 8 modulo two reproduced and delayed by 16 clock signals with a control, reference signal, which forms a register 5 (when closed by the multiplexer 15 its output with the information input), the decoder 7, trigger 18, trigger 21, and counter 14.

To obtain a control signal, it is necessary to create a control signal structure that coincides with the reproduced signal, and to form a control signal element-wise synchronously with the reproduced signal, i.e. so that the control signal matches bits with a reproducible SIGNSHOM.

The reproducible signal itself is used to form the desired control signal structure. Reproduced test signal from info | 5 output channel output

1 is fed to the information input of the delay register 4 and to the first signal input of the multiplexer 15. The control signal generation mode is switched on by the switch 16,

after the button is pressed, it switches over from the trigger 17. The output potential, the trigger signal 17 turns on the indicator 24 of this mode, opens - AND 23 to pass the signal

blocking to the corresponding input of register 4 and switches switch 15 to the state when the reproduced signal arrives at the information input of register 5. The advancement of information in registers 4 and f is performed on the front of the clock pulses of the reproduction coming from the corresponding output of channel 1.

A prerequisite for generating a pilot signal is continuous, error-free reproduction of the test signal for at least 256 cycles.

After simultaneous recording of the reproduced word into register-4 and, into register 5, decoder 7 is triggered. This denser can be complete — it decrypts the entire word recorded in register 5, or partially - tuned to a combination that does not repeat in word. This decoder 7 is connected to the outputs of the bits of the register 5 corresponding to this combination. The output signal of the decoder 7 is overwritten by the decay of this clock pulse (which recorded the last bit of the word in registers 4, 5) in trigger 18, from the output signal La which (from the positive voltage level difference) switches trigger 21. Output potential signal of trigger 21 removes blocking on the installation input from counter 14, blocks- (i.e. stops shifting) register 5, and also passes through AND 23 and blocks (stops shifting) register 4.

The counter 14 begins counting the repetition clock. At the same time, during 16 clocks from the output of channel 1, a constant pause level in the test signal arrives, which is compared at totalizer 8 with the value of the last bit of register 4 (the value of this word bit determines the value of the pause).

After 16 clocks, a signal is generated at the output of the counter 14, which resets the trigger 21 to the initial state. The lock is removed from registers 4 and 5.

Then, the next word (after this pause) is recorded in register 4 and in register 5. Errors in this case are controlled by summing up the sum0

0

five

Matrix 8 by comparing the value of the last bit of register 4, from which the previous word is derived with the value of the reproduced bit of the new word. This bit of the new word corresponds to the value of the bit of the previous word that is currently in the last (at the extreme right) bit of de register 4.

After a complete recording of the new word in register 5 (and, accordingly, in register 4), a signal is generated at the output of the decoder 7, which is rewritten into the trigger 18, the output of which switches the trigger 21 in this case. The output signal of the trigger 21 removes blocking from counter 14 and locks (stops shifting) registers 4 and 5. The error is monitored on adder 8 by comparing the level of pause coming from channel 1 with the value of the last bit of register 4, etc.

The error output of the adder 8 is rewritten to the trigger 20 to eliminate the needles present in the output of the adder 8.

Counter 13 controls the absence of errors. If, in the control signal generation mode, the output of the accumulator 8 does not have errors for 256 clock cycles, then the output of the counter 13 generates a signal that switches the trigger 19. The output signal of the trigger 19 opens the element 22 for passing the signal of the frac 7 to reset the trigger 17 to the initial state. When the next error-free word is fully entered into the register 5, a signal is generated at the output of the decoder 7, which is rewritten into the trigger 18 by the decay of the given clock pulse. The output signal of the trigger 18 passes through the AND 22 element and resets the trigger 17 to its initial state. Thereafter, the control signal generation mode ends. Moreover, this ending occurs in the middle between the information shifts in register 5,

After the trigger 17 is switched to the initial state, the indicator 24 goes out, AND 23 is locked, and multiplexer 15 connects the information input of register 5 to the output of its last bit. In this case, the register 5, the decoder 7, the trigger 18, trigger 0

five

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five

0

five

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The rep 21 and counter 14 continue to generate the control signal themselves element by element synchronously with the reproducible LR1 signal. At the same time, the output .signal of the trigger 18 also switches the trigger 21, the output of which removes the lock from the counter 14 and blocks the shift of information in the register 5 by 16 cycles, i.e. A 16-pause interval is formed between adjacent words in the control signal. After 16 clocks at the output of the counter 14, a signal is generated that resets the trigger 21 o. After this, the counter 14 is set to zero and the next 16 clocks are kept in this state, and in register 5 the word starts to circulate layer is recorded in the first bit of the register 3 after the next shift, the penultimate bit of the word is written in the first bit of register 5 with the shift of the last bit of the word 5, the second bit of register 5, etc.).

After writing the first bit of the word in the first bit of register 5, i.e. after 16 clock cycles, a signal is again generated at the output of the decoder 7, which turns on register lock 5.

Claims (1)

An elemental comparison of the reproduced signal with the reference signal is made on the Sum Gateway 8, the output error signal of which is rewritten into trigger 20. The output signal of trigger 20 (in the form of BVN) is gated with a negative half cycle of the clock signal. Error pulses are counted and indicated by an error counter, which, after completion of the formation of the control signal, i.e. before measuring errors, it is set by the operator to the zero state. Invention Formula A device for monitoring optical channel of a digital magnetic recording, containing a series-connected pulse generator, a first shift register and a control input error, connected by an output to the information input of a digital magnetic recording channel and a clock input to the output of a pulse generator, a second shift register connected between the information output of the digital channel magnetic recording and the first input of the adder, the third shift register, connect five 0 five 0 five 0 45 50 55 12 connected with the inputs of the decoder, a serially connected building element connected by a building input to the clock output of the digital magnetic recording channel and the clock inputs of the second and third shift registers, an error counter, the first pulse counter and the first trigger connected the first input through the switch to the control bus, characterized in that, in order to increase the control accuracy by taking into account the influence of the structure of the measuring signal on the synchronization accuracy of the digital channel a digital record connected to the bit inputs of the first shift register, a multiplexer connected between the information output of the digital magnetic recording channel and the information input of the third shift register connected to the second input of the adder, and the connected control unit mjiM input to the output of the first trigger and one of the inputs to the output of the last bit of the third shift register, the second, third, fourth and five triggers, the second and third pulse counters, and the first and second elements And, the second trigger is connected by the first input to the output of the decoder, the second input to interconnected syncronizing output of the digital magnetic recording channel, the first input of the fourth trigger and the first inputs of the second and third pulse counters and the output to the first input of the first one connected to each other element I connected to the output of the second input of the first trigger and the second input to the output of the third trigger, and the first input of the fifth trigger connected by the second input to the output of the third pulse counter and out the house is connected to the second input of the third pulse counter, the blocking input of the third shift register and the first input of the second element I connected to the blocking input of the second shift register and the second input to the output of the first trigger; the third trigger is connected to the first input to the output of the second pulse counter; owls and the second entrance - to the United . 3, 1510007 between themselves the second input of the second trigger, connected by the second pulse counter, the gate input to the output of the adder. element and the output of the fourth