SU1252786A1 - Device for checking logic circuits - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used to control digital and logic circuits. The purpose of the invention is to increase the depth of control. The device contains a test generator, a registration unit, a comparison circuit, three switches, an address counter, a memory unit, a reference reaction, a reference delay unit, an error counter, a mismatch circuit, a delay unit. The basic principle of control is traditional. The output response of the controlled logic is compared with the standard, and in the event of an error being detected, the address at which the error occurred is recorded. In the monitored logic circuit, individual test points are selected and signals from the output are passed through a delay unit, while signals from the test points of the standard memory unit are fed through a time delay unit to the first inputs of the mismatch circuit for comparison with the information supplied to the second inputs. Cases of mismatch are counted by the error counter and fed to the registration unit. 4 il. Q in SL

Description

The competition is related to automation and computing and can be used for control circuits.

The purpose of the invention is to increase the depth of control.

Figure 1 shows the block diagram of the device; Fig. 2 illustrates a register and a block of comparison; Fig. 3 shows an example of connection to the control points of the controlled logic through a block of time delays; on figa - time diagrams of output signals.

The device (Fig. 1) contains a generator of 1 ton pulses, a block of toasting 2, a delay element 3, a buffered drive 4, a controlled logic 5, a block of 6 time delays, a block 7 - reference time delays, a block of 8 storage of the standard, a counter 9 addresses, blocks 10 and 11 of potential matching switches 12, adder 13 over two, block 14 of recording control results, switch 15, counter 16 errors, generator 17 tests, register 18, switch 19, block 20 comparing, input 21 start.

The register 18 includes two blocks 22 and 23 of the flip-flops, the single inputs of which are connected to the outputs of the controlled logic circuit 5 (1, ..., p) and the storage block 8 of the standard 8 (1, ..., p), respectively, and the zero inputs to the output of the first phase of the generator 1 clock pulses. The number of triggers in blocks 22 and 23 corresponds to the number of outputs of the logic circuit 5 and the block In storage of standards. The unit outputs of all the triggers of blocks 22 and 23 are connected to the information inputs of the switch 19. Comparison unit 20 includes a block of 24 two-input elements And and fi, the input numbers of which are indicated by the numbers 1, 2 and 1, 2, respectively. The comparison block also includes the element lUMM 25.

The input of each element And in block 24 is connected to one of the single outputs of block 22 of flip-flops, on which the signals from the output of the control object are recorded.

The second I - -; odnch elements And block 24 are connected to the zero outputs of block 23 of the flip-flops, on which the signals from the output of the reference circuit are recorded.

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Inputs 1 and 2 of the elements And are connected respectively to the zero outputs of the block 22 of the flip-flops and to the single outputs of the block 23.

Figure 3 shows the circuits of series-connected elements 26-28 of the controlled logic circuit, delay elements 29-31, elements OR 32-34, element OR 35-37, delay element 38-40, circuits of series-connected reference storage elements 41-43. reference. The adder 13 modulo two contains the elements NOT 44 and 45, the elements And 46 and 47, the element OR 48.

The device works as follows.

Before starting work, all blocks with memory elements are returned to their initial state. Then, 1 clock pulse generator is turned on, which generates at each clock cycle and the pulses of the two phases. The first phase impulse is fed to the input of test input unit 2, and the test signals from the buffer accumulator 4 are coupled. Then, the second cycle impulses from the buffer accumulator 4 are combined at the output of the generator 1 and simultaneously fed to the inputs of the controlled logic circuit 5 and the unit 8 storing the reference, whose operation is synchronized by applying clock pulses from the clock pulse generator outputs.

The signals from the outputs of the monitored logic circuit 5 and the standard storage unit 8 are fed to the information inputs of the register 18. In the case of a discrepancy between the signals at the same outputs of the logic circuit 5 and the standard storage unit 8, the comparison unit 20 generates a fault signal, which goes to the control result recording unit I4 and at the same time, opens switch 19. Signals from the outputs of register 18, corresponding to non-coincident output signals, are fed through an open switch 19 to block 14 of the recording of control results. In case of coincidence of the signals from the outputs of the circuit 5 and the standard storage unit 8, the comparison unit 20 does not generate a fault signal and the switch 19 will be closed.

At each step of the pulse test of the first phase, the triggers of the register 18 are set to the zero state.

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as a result of this, the inputs of the elements And and And of the block 20 from the outputs of the flip-flops of the register 18 are fed from the polarized potentials. Elements And and and of block 24 are closed, and at their outputs and, accordingly, at the output of element And 1 and 25 there will be zero potentials that will not provide the opening and switch 1 9 and the supply of a fault signal to the control results recording unit.

A second phase pulse occurs: the signals are read from the outputs of the controlled logic circuit 5 and the standard storage block 8. The signals are fed to the single inputs of the triggers of the register 18 and change their state. In case of coincidence of the signals at the same outputs of the circuit 5 and the storage unit 8 of the standard, the corresponding triggers take the same state (or zero, or only 1), resulting in Both and and block 24 are supplied with oppositely distributed potentials. Comparison unit 20 does not generate a fault signal, and switch 19 is closed. In the case of a mismatch of signals at least on a pair of like-named outputs, the corresponding triggers take on different states, so the inputs of the corresponding element And or And block 24 will have unipolar positive potentials (single signals) and positive outputs will also be generated at the outputs cia; (single signal). The positive potential supplied through the element Sh1I 25 opens the switch 19, and also enters the control results recording unit as a fault signal. At the same time, through the open switch I9, the output signals are controlled in a controlled manner by the logic circuit 5 and the unit 8 for storing the standard in register 1 8.

On the next step of operation of the device, by applying a pulse of the first phase, the triggers of register 18 are again reset to the zero state, and the process of operation of the device is repeated.

From the clock 1 pulse generator inputs, the clock pulses of the first phase also go to the counting input of the address counter 9, and the second phase to the control inputs of the switch, lia the address counter 9 fixes the code corresponding to the clock

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of the circuit, which, after the end of the clock cycle, is read through the open switch 12 into the block 14 of the record

control results

5 Thus, in block 14, information is accumulated containing the cycle number, the possible fact that the monitored logic circuit 5 is not working on this clock and the output signals of the monitored logic circuit 5 and the standard storage block 8 correspond to this fault. .

The information, written 1 {in block 14, makes it possible to detect individual 15 faulty elements of the controlled logic circuit 5 with sufficient completeness of the test. However, in the case of a post-DOVLOEL connection of the malfunction elements, it becomes indistinguishable - 20 M-iMH. Therefore, in order to localize these irregularities, the device uses a block of 6 time delays and a block of 7 floors; Long time delays with contact needles 25 probes, cc) can be connected

to the control points of the controlled logic circuit 5 and the block B of storage of standards as at the beginning of npoDi pxH before oGi A malfunction spring, so 30 and rk are re-checked after the pei iici radio is indisputable. Probes subch.ch.chshgs to the control M points of the logic circuit 5 and the block 8 storage of an elliptic (Fig. 3).

 B.- ocs b and 7 delays include

1G1 delayed connected delay elements 29-31 and 38–40, which provide a delay of signals of n) cp m, longer than the passage of signals through the element, 26–28 logical cxcNibi 41–43 blocks of xsaneni standards. This ns is bypassed to eliminate the imposition of signals as they pass through delay blocks.

 Signlm from the output of each element

the delays and the corresponding control point of the element of the logical scheme 5 and block 8 are fed to the elements of the SRI 32 - 34 and 35 - 37 for exception 0

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hsr (and 1P1 detained monitors for the work of the tested circuit 5.

The outputs of blocks 6 and 7 of delays are connected through blocks 10 and 11 of potential matching, ensuring the formation and 1 pulses of sufficient duration and power to compensate for possible

the scatter of pulses on the outputs of delay blocks,

A modulo-two adder generates a single output pulse in the event of a pulse mismatch at the outputs of blocks 6 and 7 of delays.

The pulse from the output of the adder 13 modulo two is fed to the counter 16 errors, which captures the number of mismatches of pulses from the outputs of the delay blocks. After the test is completed, the signal from the output of the sign of the end of tests of the test generator is fed through element 3 of the delay to the control inputs of the switch 15 and opens it. A code corresponding to the number of non-coincident pulses of the bit outputs of the error counter 16 is fed through an open switch 15 to the control results recording unit 14, from which it can then be printed on a paper tape. through blocks 6 and 7 of the delay, after the end of the test signals,

According to the number of mismatched pulses at the outputs of blocks 6 and 7, it is possible to determine the malfunction) of the first element of the series-connected elements 26-28 (41-43). For example, let the element 26 of the circuit 5 be faulty. In this case (single or zero pulses) at the output of the cells of this element, as well as the other elements 26-28, as a rule, do not coincide with the output signals of the corresponding elements of the unit 8 stored and reference As a result, the total number of mismatches recorded by the counter 16 is an error of 3 and corresponds to a malfunction of the element 26 (FIG. Yes). If the element 27 is faulty, then the signals at the outputs of the elements 27 and 28 do not coincide (Fig.). As a result, the number of mismatches is 2, which corresponds to the malfunction of the element 27 and t, d. Thus, by the number of discrepancies recorded by the counter 16 errors and allowed to print by block 14 of the recording of control results, it is possible to approximately estimate the location of the fault in the circuit of series-connected elements,

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A device for controlling logic circuits containing a test generator, a standard storage unit, an address counter, a compared block, an error counter, the first switch, with the B.1 approach of the test generator test set connected to the counting

the input of the address counter, the start-up input of the device is connected to the start-up input of the test generator, characterized in that, in order to increase the control depth, it contains a block of time delays, a delay element, a block of reference time delays, two blocks of potential matching, modulo adder, register , the second and third switches and the control results recording unit, where the output of the test generator test feature set is connected to the reset inputs of the control unit of the standard storage unit and the register, as well as to the input ohm readout of the control results recording unit, the output of the polling generator of the test generator is connected to the synchronization inputs of the monitored logic circuit, the standard storage unit, the control input of the first switch and the recording input of the monitoring results recording unit, the output of the polling indicator of the total number of test generator mismatches is connected to the control input of the second switch, the outputs of the characteristic of the test set of the test generator are connected to the information inputs of the controlled logic circuit and the storage location of the reference, the outputs of which and the outputs of the controlled logic circuit are connected to the information inputs of the register, the first and second groups of outputs of which are connected to the first and second groups of information inputs of the third switch and the first and second groups of information inputs of the comparison unit, the output Not equal to which is connected to the control input of the third switch and the synchronization input of the control recording unit, the bit outputs of the address counter are connected to the information H1,1 inputs of the first switch torus kotorog group of outputs and a group of second and third outputs commutative

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tori are connected to the first, second and third groups of information inputs of the control results recording unit, the outputs of which are connected to the information outputs of the device, the outputs of control points of the controlled logic circuit are connected to the inputs of the time generating unit, whose output is connected to the first through the first potential matching unit the entrance sum52786

modulo two, the output of which is connected to the counting input of the error counter, the bit outputs of which are connected to the information inputs 5 of the second switch, the outputs of the reference control points of the standard storage unit are connected; ::: are connected to the inputs of the unit of the standard time delays whose output is connected to second 10 input modulo two.

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Editor V. Petrash

Compiled by A.Sirotska Tehred V.Kadar

Order 4621/49 Circulation 671 Subscription

VNIIPI USSR State Committee

on inventions and discoveries 1G3035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

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FIG.

Proofreader I. Muska

Claims (1)

Claim A device for monitoring logic circuits, containing a test generator, a reference storage unit, an address counter, a comparison unit, an error counter, a first switch, and B (11th input of the test set of the test generator test is connected to a counting 10 input of the address counter, the device start input is connected to the input test generator start-up, characterized in that, in order to increase the depth of control, it contains a block of time delays, a delay element, a block of standard time delays, two blocks of potential matching, an adder modulo two a, a register, a second and a third third switches and a block for recording the results of control, the output of the test set of the test generator test connected to the reset inputs of the controlled logic circuit 25 of the storage unit of the standard and register, as well as with the read input of the block for recording the results of the control, the output of the polling generator of tests is connected to the synchronization inputs of the controlled logic circuit, the standard storage unit, the control input of the first switch and the recording input of the recording unit for recording the monitoring results, the output of the polling indicator the number of mismatches of the test generator through the delay element is connected to the control input of the second switch, the outputs of the test set of the test generator of the test are connected to the information inputs of the controlled logic circuit and the storage unit of the reference, the outputs of which and the outputs of the controlled logic circuit are connected to the information inputs of the register, the first and second groups the outputs of which are connected to the first and second groups of information inputs of the third switch and the first and second groups of information inputs of a comparison, the output of Not equal to that is connected to the control input of the third switch and the synchronization input of the control results recording unit, the bit outputs of the address counter are connected to the information inputs of the first switch, the group of outputs of which and the group of outputs of the second and third switches 7 are connected to the first, second and third groups of information inputs of the control results recording unit, the outputs of which are connected to the information outputs of the device, the outputs of the control points of the controlled logic circuit connected to the inputs of the time delay generation unit, the output of which through the first potential matching unit is connected to the first input of the adder modulo two, the output of which is connected to the counting input of the error counter, the bit outputs of which are connected to the information inputs 5 of the second switch, the output of the reference control points of the reference storage unit are connected to the inputs of the reference time delay unit, the output of which is connected to the second 10 input of the adder modulo two. FIG. 1 FIG. 2 1 252786 UX 6 t --------------1------------------ 1 N 1 ι 1 ι ι ι I 1 ή ιίιί t 2 1 Y 6 0 L — Ί I I  1 eleven l 1 1 JL t eleven fib 2 1 _a t FIG. 9