SU1520518A1 - Device for diagnosis of logical units - Google Patents

Abstract

The invention relates to automation and computing and can be used to monitor the health and search for defects in logical blocks of RAM. The purpose of the invention is to increase the reliability of the control. The device contains a generator of 1 pulses, the unit of test 2, the control unit 3, the display unit 4, two blocks 5, 6 And elements, the block 7 comparison. Before starting the diagnostics, zero information is recorded in all the RAM cells. For the organization of diagnostics, a cycle of accessing one RAM cell consisting of three stages is used: the first stage is reading the stored information, the second stage is writing information to the selected RAM cell, the third stage is reading the information recorded at the second stage. The positive effect is determined by the introduction of the comparison unit and the corresponding test master structure. 8 il.

Description

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The invention relates to automation and computing and can be used to monitor the health and search for defects in logic blocks.

The aim of the invention is to increase the reliability of the control.

Figure 1 presents the block diagram of the proposed device, figure 2 is a diagram of the unit tests; FIG. 3 is a diagram of a control unit; FIG. 4 is a diagram of an address generator; 5 is a pseudo-random sequence generator circuit; FIG. 6 is a diagram of a synchronization node; FIG. 7 is a diagram of a first pulse distributor; FIG. 8 is a diagram of a second pulse distributor.

A device for diagnosing logic blocks (Fig. 1) comprises a pulse generator 1, a test setpoint generator 2, a control unit 3, an indication unit 4, two blocks 5 and 6 of elements AND, a comparison block 7 and a monitored block 8.

Test master .2 tests (figure 2) contains. address generator 9, four blocks And 10-13 elements And, register 14, counter 15, comparison block 16, frequency divider 17, pseudo-random sequence generator 18.

The control unit 3 (Fig. 3) contains a trigger 19, the node 20 is synchronized. nizatsii, two dividers 21 and 22, the node 23 forming the initial conditions, the counter 24, two elements OR 25 and 26, the generator 27 of a single pulse, two decoders 28 and 29, two elements 30 and 31 delay.

ten

15

20

25

thirty

35

pulses, the elements OR 56 and 57 and the element AND 58.

The distributor 54 pulses (Fig contains a trigger 59, the elements And 60-64, the delay element 65, the element AND NOT 66.

The distributor 55 pulses (Fig. Contains the item NOT 67, the elements And 68-71, the counter 72, the delay element 73 and the decoder 74.

A device for diagnosing logical blocks operates as follows.

Using the controls, node 23 sets the cycle number code (CCL), i.e. the number of initial states of the generator is 9 addresses in the unit of 2 tests. In addition, from the control unit 3 to the setter of 2 tests, it sends from the location code a zero combination (CMNC) in the generator 9 addresses of the setter of 2 tests.

Using the controls of node 23, a Start command is issued, which is used to start the operation of the entire device.

At the start command, the control unit 3 performs the following operations:

a) generates a signal PGI-start generator clock pulses, after which the clock pulses from the generator

1 pulses are fed to the setter of 2 tests and to the synchronization unit 20 of the control unit 3;

b) simultaneously with the PGI signal, the signal Set. O is set to the state O of the divider 21, This state is decrypted and at the output of LH 1 of the decoder 29 appears once, P1 q J, C1 JTi f, f - tty - Jt ", ™ -.--. Y . - -. .-- "- - .- -, -, - f, -. F

The address generator 9 (FIG. 4) contains the signal that goes

there is a delay element 32, an element 33, a reversible generator 34 of a pseudo-random sequence, a block 35 of elements AND, a reversible counter 36, a block 37 of comparison, a register 38 and a trigger 39.

The pseudo-random sequence generator 18 (FIG. 5) contains b & ase cells 40-43, elements AND 44-47, element NOT 48, elements OR 49-51, adder 52 modulo two, trigger 53.

The reversible pseudo-random sequence generator 34 is made in the same way as the generator45

50

on node 20 sync,

C) with a delay relative to the signal of the PGI generates a signal recording ZP}, which enters the unit 2 test. According to the signal ZP 1, the initial state of the 9 addresses generator is stored in the test unit 2;

d) with a delay relative to the PIP signal greater than for the signal of the RFP 1, the signal of the recording of the RF2 2 is input, which enters the unit of the 2 tests. By the signal of the RF2, the generator

9 addresses record the initial state that was memorized by

the torus 18 pseudo-random sequence of the 55g signal of the RFP 1;

nosti.d) simultaneously with the signal RFP 2

The node 20 synchronization (Fig. 6) co-generates a signal RZTI-- signal

holds two allocators 54 and 55 im pass permit them

five

0

five

0

five

pulses, elements OR 56 and 57 and element AND 58.

The distributor 54 pulses (Fig.7) contains the trigger 59, the elements And 60-64, the delay element 65, the element AND-NOT 66.

The distributor 55 pulses (Fig.8) contains the element NOT 67, the elements And 68-71, the counter 72, the element 73 delay and the decoder 74.

A device for diagnosing logical blocks operates as follows.

Using the controls of node 23, a cycle number code (CCL) is established, i.e. the number of initial states of the generator is 9 addresses in the unit of 2 tests. In addition, from the control unit 3, the zero combination location code (CMOS) in the generator 9 addresses of the master of the 2 tests is fed to the unit of the 2 tests.

Using the controls of node 23, a Start command is issued, which is used to start the operation of the entire device.

At the start command, the control unit 3 performs the following operations:

a) generates a signal PGI-start generator clock pulses, after which the clock pulses from the generator

1 pulses are fed to the setter of 2 tests and to the synchronization unit 20 of the control unit 3;

b) simultaneously with the PGI signal, the signal Set. O is set to the state O of the divider 21, This state is de-encrypted and at the output of LH 1 of the decoder 29 appears rasLJ-, ™ -.--. In J. - -. .-- "- - .- -, -, - f, -. F

on node 20 sync,

C) with a delay relative to the signal of the PGI generates a signal recording ZP}, which enters the unit 2 test. According to the signal ZP 1, the initial state of the 9 addresses generator is stored in the test unit 2;

d) with a delay relative to the PIP signal greater than for the signal of the RFP 1, the signal of the recording of the RF2 2 is input, which enters the unit of the 2 tests. By the signal of the RF2, the generator

The 9 addresses are recorded in the initial state, which was memorized by

51

pulses per node 20 sync. Oigial RZTI enters the node 20 synchronization.

Next, an O is written to the cells of the checked block 8 when the addresses are changed in the forward direction. Signals of RFP, SCh2, Zp / MF, PCRV are set equal to O, ZP signal is fed to the unit of 2 tests and sets the value of the reference response to O. The signal of the MF enters the unit of 2 tests and sets the value of the recorded information to O. on blocks 5 and 6 of the elements And and on the checked block 8 and sets the recording mode. The signal РРРВ arrives at blocks 5 and 6 of the elements AND, and prohibits the passage of signals through them. With the arrival of the next clock pulse in the synchronization node 20, a negative OCR pulse is generated. This pulse is used to record information in the checked block 8.

If the address enumeration is not completed, then with the arrival of the next clock pulse, a positive pulse-SDB is generated using the synchronization node 20. The ADD pulse enters the test driver 2 and causes a change in the address at which information will be recorded.

If the address search is completed, the SRB signal is generated in the test probe 2, which is fed to the control unit 3. The SRV signal is taken into account when counting the initial states of the generator 9 addresses in the test generator 2. In the divider 21, the SRV signal causes a change of state and the decoder 29 generates a LH signal 2. At this, the device switches to the test mode of the memory cells of the tested block 8. For this, the synchronization node 20 generates the necessary signal sequences PCRV, RZZS, Pn / MF, RFP, MF 2. A three-time reference is made to the tested block 8. First, it reads the information contained in the cell from the cell, compares the response of the transmitted block 8 with the reference response (ESM) generated by the test generator 2 (ESM) 0).

Further, the address is not changed; information is recorded;

18

18 generators of the test setpoint generator 2 tests, in test unit 8, the comparison between the PR and the ESM is not made.

When the memory cell is accessed for the third time, the newly recorded information is read and the PR and ESM are compared.

If the check of all memory cells has passed successfully and the search of addresses in the forward direction is completed, then the transition to the search of the same addresses is performed in the strictly opposite direction. In this case, in the test generator 2, the PN signal is sent to the reverse signal and the address generators 9 and 18 and the SRP, respectively, will change their state in a strictly reverse sequence.

If the check of the memory cells in one initial state of the generator. 9 addresses in the forward and reverse directions of the address change was successful and there were no failures, then the new initial state of the address generator 9 is set and memorized. This unit of control 3 with the arrival of the corresponding signal of the SRV produces a sequence of signals yoke, ZP 1, ZP 2.

The check of the end of the initial states is performed in control unit 3.

If any of the comparison between OP and .EPA revealed incomparison, then Comparison Unit 7 generates an NCPB Comparison signal, which goes to Control Unit 3.

 The control unit 3 generates an IISP-signal - it is faulty, which is fed to the display unit 4, and the sgi signal.

The display unit 4 generates a message Faulty and reports the address at which the error occurred.

Unit 2 tests (Fig. 2) works as follows.

In the initial state, i.e. After turning on the power, the address generator 9 and the memory band generator 18 are arbitrary: the zero value of the signal is present at the output of the frequency divider 17, and the clock pulses (TI) arrive at the counter 15 from the pulse generator 1, which account for the change in the count state

71

Chip 15. From the control unit 3, the zero combination location code (CMNK) is written to the address generator 9, which determines the zero position in the SRP position, i.e. the place of the zero address in the address sequence. Then, according to the signal ZP 1 from the control unit 3, the block 12 of elements AND opens and the state of the counter 15 through the block 12 elements And is recorded in the register 14. Then, according to the signal ZP 2 from the block 3 of control, first of all, the unit 10 opens And the contents of the register 14 enters the address generator 9, from where the address (ADR) from the comparison unit 16 arrives, to the indication block 4 and to the checked block 8, secondly, the address generator 9 is set to a working state. Then, according to the signal from the control unit 3, the test generator sets test results from the contents of the generator 18 of the SRP: first, through the block of 11 elements, And a nonzero reference response (ESM) to the block 5 of the And elements, secondly, through the block 1 elements and the zero test set (TH), which is fed to the tested block 8. Then, by the signal of the MF 2 from the control unit 3, a zero EOR and a nonzero TH are formed. Then, according to the ADD signal, information is shifted in the generators of 9 addresses and 18 SRPs. After that, the operation of the setter 2 of the tests is repeated according to the signals of the CC, SC2, VLT. If the information output of the address generator 9 appears null, the combination, then at the control output, the RZS signal — a comparison resolution arriving at the comparison unit 16 — is received. If the contents of the initial state register are equal to the address at the output of the address generator 9, then at your progress of the comparison block 16 a signal of the SRV appears: first, first to the control unit 3, and second to the frequency divider 17. Each second SRV signal causes a change in the direction-change signal (PN) at the output of the frequency divider 17. This signal arrives at address generators 9 and 18 of the memory bandwidth and causes a change in the direction of shift of the contents of these generators.

After checking the tested block 8 in the first initial state, the operation of the test setter 2 is repeated.

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signals TI, ZP 1, ZP 2, 311, MF 2 and

ADD.

The generator 9 addresses (Fig. 4) works as follows.

From control unit 3, register KMNK-38 is the location code of the zero combination in the memory bandwidth. Then, control unit 3 receives the signal 2, which zeroes the counter 36 and the trigger 39. At the same time, the HC — the initial state from the register 14 initial states is written to the generator 34 of the SRP through the block 10 of the elements I. Then from block 3 control receives impulse ADD, which, first, increases by one the contents of counter 36, secondly, after a time sufficient to change the contents of counter 36 and determined by delay element 32, enters through element 33 as delayed impulse ADD to the SRP generator 34 and cheating Em the contents of this generator. If the contents of counter 36 are equal to CMNS memorized in register 38, then at the output of comparison block 37, a zero NCPB signal appears, which, firstly, sets the trigger 39 to one unit, the forward output signal of which appears block 16 compares, secondly, closes block 35 of the elements AND, and provides a zero combination in the SRP, thirdly, enters the input of element AND 33 and prohibits the passage of the ADD pulse to the generator of the SRP 34, thus avoiding the loss of the current state generator. The next ADD pulse changes the contents of the counter 36, a unit appears at the output of the comparison block 37, the AND element block 35 and the AND element 33 opens and the current state appears at the output of the PSP 34. If the PSP 34 generator is returned to the initial state, then the frequency divider 17 receives a PN signal, which, firstly, is fed to the counter 36 and transfers it from the summation mode to the subtraction mode, secondly, it goes to the PSP generator 34 and changes the direction of the information shift. After that, the operation of the address generator 9 is repeated in the reverse enumeration of the generator of the SRP 34.

Claims (1)

Invention Formula A device for diagnosing logic blocks, comprising a pulse generator, test setter, control unit, display unit and two AND units, the start and stop inputs of the pulse generator are connected to the corresponding outputs of the control unit, the group of synchronization outputs of which are connected to the group of corresponding inputs of the test setter, the first group of information outputs of which is a group of information outputs of the device for connecting to the group of information inputs of the monitored unit, - in order to increase the reliability of the control, a comparison block is entered into it, the group of address outputs of the test setter is connected to the group of information inputs of the display unit and is the group of address outputs of the device to be connected to the group of address inputs of the monitored block, the second group of information - the on-line outputs of the test setter are connected to the group of information inputs of the first block of elements I, the first input of which gating is combined with the first input of the gating of the second block in AND and connected to the output of the comparison of the control unit, the write-read output of which is connected to the second gating inputs of the first and second blocks of the AND elements and is the write-read output of the device to be connected to the write-read input of the monitored block is the output of the device for connecting to the recording input of the monitored block, the group of information inputs of the device for connecting the output group of the monitored block is connected to the group of information inputs in the second block of elements And, the output GRUPP of which is connected to the first group of inputs of the comparison unit, the second group of inputs of which is connected to the group of outputs of the first block of elements And, the group of control inputs of the display unit is connected to the group of outputs of the address of the faulty point of the control unit connected to the output ten 15 20 25 thirty 35 40 45 50 55 1810 the inequality house of the comparator unit, the beginning of the control unit control cycle input is connected to the corresponding output of the test unit, the synchronization input of which is combined with the synchronization input of the control unit and connected to the output of the pulse generator, the control unit contains a synchronization node, an initial condition generating unit, two dividers, two a decoder, two OR elements, a counter, a single pulse generator, a trigger and two delay elements, the input of a sign of a malfunction of the block connected to the first input of the first The OR element is the output of the Faulty control unit, the output of the first decoder of which is connected to the second input of the first OR element and is the output of the healthy block, the input of the first decoder is connected to the information output of the counter, the group of information inputs of the formation node initial conditions, the second group of outputs whose initial conditions, the group of outputs of the synchronization node and the outputs of the first and second delay elements form a group of outputs b The synchronization of the control unit, the start output of the single pulse generator of which is connected to the inputs of the first and second delay elements, with the installation input of 1 flip-flop, the installation input of the first divider and the output of the single pulse generator, whose input is connected to the output of the second element OR The first input of which is combined with the synchronization input of the counter and connected to the output of the second divider, the synchronization input of which is combined with. the synchronization input of the first divider and is the input of the beginning of the control block: control, the synchronization input of which is connected to the input of the synchronization node, the first AND second inputs of the mode of which are connected respectively to the first and second outputs of the second decoder, the input of which is connected to the output of the first divider, the second and the third outputs of the synchronization node are respectively the write-read, compare resolution, and write enable resolution of the control unit, the output generator of the single pulse generator which is connected to the output of the first element OR, the second input of the second element OR is connected to the start output of the initial conditions formation unit, the output of the second delay element is connected to the installation input to the trigger, the inverse output of which is connected to the trigger input of the synchronization node, and the test generator contains the address generator , pseudo-random sequence generator, comparison unit, counter, register, divider, and four blocks of AND elements, with the output generator group of the address generator connected to the first input group block test driver is a group of test output driver outputs, the output of the beginning of the monitoring cycle of which is connected to the equality output of the test driver comparison unit and the input of the test driver divider whose output of the divider is connected to the inputs of the operation mode of the address generator and pseudo-random sequence generator whose shift inputs combined and connected to the group of inputs of the synchronization of the test master, the first group of information outputs of which is connected to the group of outputs of the first block And ementov setpoint tests input group of AND gates of the first block which is connected to a group of outputs. pseudorandom sequence generator and with a group of inputs of the second block of test driver settings And, a group of outputs of the second block of elements And which is the second group of information outputs of the test generator, the synchronization input of which is connected to the counting input of the counter of the test generator, and a group of information outputs of the counter of which are connected to the group of inputs the third block of elements and test driver, the group of outputs of the third block of elements and which is connected to the group of inputs of the test master register, g The register outputs of which are connected to the second group of inputs of the benchmark comparator unit and the input group of the fourth block of elements I, whose input is connected to the setup input of the address generator and connected to the group of clock master input inputs of the test benchmarking unit is connected to the permission output five 0 five 0 five 0 five 0 five compare the address generator, the group of information inputs of which are connected to the group of outputs of the fourth block of elements And, the inputs of the first, second, third blocks of elements And the test setter and the group of inputs of the initial conditions of the address generator together with the input of the fourth block of elements And and the shift input of the address generator and pseudo-random generator the sequences form a group of inputs of the master of the test set up, the address generator contains a reversible pseudo-random sequence generator, a reversible counter, a comparison block, a register, a trigger, a block of elements AND, an AND element and a delay element whose output is connected to the first input of the AND generator of the address generator, an element output And which is connected to the input of the reversible pseudo-random sequence generator, the group of outputs of which is connected to the group of inputs of the block of elements AND of the addr generator sa, the shift input of which is connected to the input of the delay generator of the address generator and the counting input of the reversible counter, the output group of which is connected to the first group of inputs of the address generator comparison unit, the installation input of which is connected to the installation input of the reversing counter and the installation input O of the address generator trigger, the group of informational inputs of which is connected to the group of inputs of the reversible generator of a pseudo-random sequence, the mode input of which is connected to the input of the reversible mode The counter is the input of the address generator operation mode, the input condition group of which is connected to the address generator input address group, the output register register of which is connected to the second input address comparison unit group, the noncomparison output of which is connected to the installation input 1 flip-flop, with an input of the block of elements And, and with a BTopbiM input of the element And the address generator, a group of outputs of the block of elements And of which is a group of outputs of the address generator, the output of the trigger of which L is output enable comparison of address generator. ff / 7fff 7 HCPB from. Ul. from 6A, P Ta L. ICP:, g. K5LL 5,6,6  K6 / i.Sf.6  .KS / t.8 Fig.Z OT / .nnm t f 7 from fa. 3 one ja ... j FIG 5 XSA.2 FI.6 k59 RZZS ttSf 7 "Si § c Compiled by I.Ivanykin Editor V. Bugrenkova Tehred L.Serdyukova Proofreader L.Beskid Zakae 6759/50 Circulation 668 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., A / 5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 . ( "§I§ H Subscription