SU1198538A2 - Device for generating histogram of random numbers - Google Patents

Abstract

DEVICE FOR THE FORMATION OF HISTOGRAM OF RANDOM NUMBERS on the author. St. No. 995097, characterized in that, in order to expand the functionality of the processing of time intervals, it contains two delay elements, a group of AND elements, a counter and a BAN element, the direct input of which is connected to the output of the clock source, and the inverse input of the BAN element connected to the inputs of the first and second delay elements, to the first inputs of the elements AND of the group and is the input of the measured time intervals of the device, the output of the BAN element is connected to the counting input of the counter, the outputs of which are th connected to second inputs of the AND sootvetstvuk Tsikh group, the outputs of which are connected with. the inputs of the corresponding bits of the memory register, the output of the first delay element is connected to the Reset counter input, the output of the second delay element is connected to the counting input of the O-number counter, histogram formations, and the first input (N + l) -ro with the second inputs of elements I. § CD 00 SP 00 00

Description

one

The invention relates to computing and can be used to analyze the distribution of time intervals between the instants of random events simulated by standardized amplitude and duration pulses in the physical modeling of problems in the theory of mass service and the theory of random flows.

The aim of the invention is to expand the functionality of the device by processing time intervals.

The block diagram of the device shown in the drawing.

The device contains a receive register 1, N registers 2 interval boundaries, N comparison circuits 3, two groups of elements AND 4, 5, (N +) accumulative counters 6, counter 7 of the number of histogram generation, counter 8 measurements, element 9 Disable, elements 10 and 11 delays, inputs 12-15.

The device works in the following way.

In the initial state, registers 2 recorded the values of the boundaries of the histogram intervals a ,, aj, ..., aj, ...,

counters 6 and 7 are set to

N

O. state

Signals arrive at the input of the device 15, the time intervals between which arrivals are subject to analysis. The beginning of the measurement corresponds to the connection time of the clock generator.

When the first signal arrives at the input 15, the contents of counter 8 are overwritten into the receive register 1 and the counter 8 is reset. The reception register records the code of the time interval from the beginning of the experiment to the first signal

Let this code belong to the interval o, a (, then, due to the condition (x, t,) from the first output of the first comparison circuit, the resolving potential is fed to the input of the first element 4. The input signal delayed by the delay element 11 is fed to the input of counter 7 the input of the first reader 6. The same signal, fed to the inverse input of the element 9, prohibits the passage of clock pulses during the rewriting of information from the counter 8 to the re-

85381

history I, then sets counter 8 to the zero state.

At the end of the inhibitory effect of the first signal, element 9 is open

5 and the clock pulses are fed to the input of the counter 8. Such processes are carried out before the arrival of the second signal, which rewrites the contents of the counter 8 into the receive-

About nyy register 1 as described above. Let the time interval code Xj written in the receiving register 1 from the first to the second signal belong to the interval of the number axis

S a ,, a. In this case, there will always be two adjacent schemes 3 of comparison with the numbers i - 1 and i (i 2, 3, ..., N), which establish the fact of the truth of the inequalities Gh, -c aO and (k "a-,

   I I 2 1-1 /}

0 in this case, from the second output of the first and from the first output of the second one, the resolving potentials are supplied to the two outputs of the 1st element And 4. Delayed by delay element 11

5, the signal from the input 15 of the device enters the input of the counter 7 and through the open i-th element I 4 - to the input of the ith counter 6, increasing by one the contents of these counters.

0 Upon arrival at the input 15 of the device of the third signal, processes similar to those described above are carried out. Let the X-interval time code recorded in the receiving register 1 be from

5 of the second to the third signal belongs to the interval of the numerical axis a) d, de M - the digit of the register 1). Moreover, due to the fulfillment of conditions (x, a „) at the second input of the N-th circuit 3

0 comparisons are formed and fed to (K + 1) -th element AND 4 resolving potential. The signal delayed by the delay element 11 from the input 15 of the device passes to the input of the counter 7 and through the open (Y + 1) -th element I 4 to the input () of the counter 6, increasing by one the contents of these counters.

Thus, with the arrival of each signal, the content of the counter 7 and the corresponding interval of the counter 6 are increased by one unit. This is how the histogram of the time intervals 5 between the instants of the distribution of random events is formed.

The processes of forming a histogram of random numbers do not differ from

jtpoiieccoB, occurring in the prototype, with the information input 13

Devices arrive at random numbers.

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Claims (1)

DEVICE FOR FORMING A HISTORY OF RANDOM NUMBERS by ed. St. No. 995097, characterized in that, in order to expand the functionality, it allows processing of time intervals, it contains two delay elements, a group of AND elements, a counter and a FORBID element, the direct input of which is connected to the output of the clock source, and the inverse input of the FORBID element is connected to the inputs of the first and second delay elements, to the first inputs of the AND elements of the group and is the input of the measured time intervals of the device, the output of the BAN element is connected to the counting input of the counter, the discharge outputs of which are lyucheny to respective second inputs of the AND group, the outputs of which are connected with. the inputs of the corresponding bits of the memory register, the output of the first delay element is connected, is dined with the Reset input of the counter, the output _of the second delay element is connected — SS is not with the counting input of the counter of the number of histogram formations, with the first input of the (N + 1) -th element And with the second inputs of the elements I.