SU913394A1 - Statistic analyzer - Google Patents

Description

The invention relates to computational ^{1 *} tion engineering and can be used for statistical studies of stochastic processes, namely to determine the extrema of the distribution density. ^{3 * * * * * *}

Known statistical analyzer comprising a comparator, down counter, an analogue-code converter, the two groups of coincidence circuits, two groups of lines ¹⁰ zaderzh-

ki, waiting for multivibrators, trigger, collective circuit, pulse generator, decoder, channel coincidence circuit, counting indicator

devices, and allowing to measure the density distribution of extrema [11.

However, this device does not provide protection from interference, the amplitude

which exceeds the quantization level.

The closest in technical essence and functionality to the invention is statis2

tic analyzer containing a group of comparison elements, the first inputs of which are combined and are the input of the analyzer, the second input of each comparison element is the corresponding control input of the analyzer, a group of pulse shapers, the output of each comparison element of the group is connected to the inputs of two group of pulse shapers connected respectively to the inputs of the first element OR, and the outputs of the odd group of pulse shapers connected to the inputs of the second element ENT, the output of the first element OR is connected to one of the trigger inputs, and through the first delay element with the subtracting input of the reversing register, the output of the second element OR is connected to another input of the trigger, and through the second delay element with the summing input of the reverse register, bit outputs

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reverse register connected respectively to the inputs of the first group of the decoder and the bit inputs of the register, the outputs of which are connected respectively to the inputs of the second corpus of the decoder, the outputs of which are connected to the inputs of the memory block and, accordingly, the outputs of the trigger are connected to the control inputs of the register and the decoder respectively [2] . ten

The disadvantage of this device is its low noise immunity, since all interference, the amplitudes of which exceed the sampling value, are processed by the analyzer as 15 real signal, which distorts the received information and introduces an error into the analysis results, reducing its reliability.

The purpose of the invention is to increase the reliability of the analysis by eliminating false pairs of extrema.

This goal is achieved by the fact that the statistical analyzer _containing a group of comparison elements, the first inputs of which are combined and are the information input of the analyzer, the second input of each comparison element is the corresponding control input of the analyzer, the group of pulse shapers, the output of each comparison element of the group is connected to the inputs two pulse shapers group yields even pulse shaping group ³⁵ · are respectively connected to the inputs of the first OR gate, and outputs odd f rmirovateley pulse groups respectively connected to the inputs of a second OR gate, an output of first OR gate connected to one of the trigger inputs, and through a first delay element - to a subtraction input of the first down counter, the output of the second OR gate is connected to another ⁴⁵ entry trigger, and by the second element delays with a summing input of the first reversible counter, the bit outputs of which are connected to the inputs of the first memory register ^50, respectively, the bit outputs of which are connected to the information inputs m of the first decoder, respectively, the outputs of which are connected respectively to the inputs of the first corpse of the memory unit ⁵⁵ , further comprises a second decoder, a second storage register, a second reversing

a counter, two AND elements, a digital comparison circuit and an additional OR element, and the inputs of an additional OR element are connected respectively to the trigger output and the first inputs of the corresponding AND elements, the output of the additional OR element is connected to the setup input of the second reversible counter, the subtracting input of which is connected to the output of the first the delay element, the summing input is connected to the output of the second delay element, and the bit outputs of the second reversible counter are connected to the inputs of the first group of digital Comparison circuits, respectively, whose output is connected to the second inputs of both elements AND, the output of the first element AND is connected to the control input of the first storage register, the control input of the second decoder and the installation input of the second storage register, the output of the second element AND is connected to the control input of the second storage register, with the control input of the first decoder and the installation input of the first storage register, the bit inputs of the second storage register are connected with the digit outputs n the first- down counter respectively, outputs of second bit storage register connected to the data inputs of the second decoder, respectively, the outputs of which are connected respectively to the inputs of the second group of the storage unit, the second group of inputs a digital comparison circuit is further analyzer inputs.

FIG. 1 shows a block diagram of a statistical analyzer; in fig. 2 - time diagrams explaining his work.

The statistical analyzer contains a group of comparison elements 1 (n is the number of quantization levels), a group of drivers 2 (2 * - 2 <2 _P ) pulses, two elements OR 3, (3 <3 c) trigger 4, an additional element OR 5, two delay elements 6 (6η-6η) reversible counters 7 and 8 digital ¹ comparison circuit 9, two elements AND 10, (10 _and -10 (^) two registers Ί1 (11 ^ -11 ^) two decoders 12 (12 _η -12 ^) , memory block 13, additional inputs 14 of the analyzer.

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In memory block 13, there are two groups of counters in which information is accumulated on the number of maxima and minima at quantization levels. The inputs 14 are fed a number, 5 equal to the value of the boundary amplitude, with which the number is compared from the output of the reversible counter 7. Before starting work, the triggers 4 are set, the reversible counters, 0 and 7 and 8, the registers 11 ₁ and 11 ^, and Circuit 9 is written to the code of the boundary amplitude.

The analyzer works as follows. 15

The random process under study, entering the analyzer input, is, as it were, divided into η quantization levels, according to the number of comparison elements 1, to the first inputs of which an input signal is fed, and to the second - reference voltages. Zero signal is combined with the first level of quantization. Elements 1 comparison produce voltage drops. When moving 25

the input signal through the quantization level from bottom to top at the output of the element 1 comparison of this level appears a positive voltage drop, and when going from top to bottom - 30 negative. The formers of 2 pulses form the pulses according to these drops, and the even formers 2ιχ, 2 ^, ..., 2 ^ form the pulses for the negative differences, and the non-even 35formers 2 ^, 2. .2ι ^ _η _ / (positive. When the input signal is increased, pulses from the outputs of the odd formers 2 will be sent to the corresponding inputs of the element OR 3 ^ and when it decreases from the outputs of the even drivers 2 to the corresponding inputs of the element OR Z _l And these pulses are equal to the number of levels crossed by the 45th signal. The pulses from the output of the OR 3 element (1 are summed in the reversible counter 8, and the pulses from the output of the OR 3> element are subtracted. Thus, the level number code is formed in the reversible counter 8 on which in this oment is si | - cash This code is proportional to the amplitude extreme..

When the input signal changes from * the outputs of the elements OR 3, the pulse sequences will be received in succession corresponding to the increase in

or descending signal. Prymem the first pulse of each sequence is a sign of extremum, and the code of the level number on which it occurred is formed in the reversible counter 8, after the arrival of the last pulse of the previous sequence | Ti. Thus, the first pulse of a sequence from the output of an element OR 3 ^ 1 is a sign of a minimum, and the first pulse of a sequence from the output of an element OR 3 ^ "is a sign of a maximum.

Each interference received at the input of the statistical analyzer introduces false extremes into the process under study (see Fig. 2, where a is the process under study; b is interference; 9 is the signal at the analyzer input). By processing in a special way all the extrema of the input signal, the analyzer, as it were, catches those of them, which are κοτοροίε caused by interference. The main feature is their amplitude. The boundary amplitude is set in advance and is selected in accordance with the amplitude of the prevailing interference. The boundary amplitude is taken as a multiple of the width of the differential corridor. The code of the boundary amplitude is written in the scheme 9 · ·

The interference (both positive and negative) causes a false extreme “maximum-minimum” pair as the signal under investigation increases.

(in Fig. 2, 8- points "4", "5 '% and when it decreases - a false extreme pair" minimum-maximum "(in figure 2, points" 7 "," 8 "). Therefore, when the statistical analyzer is used, the ratio of two adjacent extremes.

I.

The first pulse of each sequence sets the trigger 4 to the opposite state. In this case, a pulse to the element OR 5 and to the corresponding element AND 10 arrive at the corresponding pulse output of the trigger 4. The subsequent pulses of this sequence do not change the state of the trigger 4. Thus, the trigger 4 produces a pulse on the first pulse of each sequence.

The code of the difference between the amplitudes of two adjacent extrema is formed in the reversible counter 7 · When

of extremum (a sign of which is the first impulse of each subsequent

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sequence), a pulse from one of the pulse outputs of the trigger 4 through * the element OR 5 resets the reversible counter 7 to zero. When the signal reaches the next extremum in the reversible counter 7, a code is accumulated that is proportional to the difference of the amplitudes of the previous and the given extremum. If this difference is greater than the specified one, then the comparison circuit 9 gives 1 permission to the AND 10 elements.

In register 1¼, the code of the level number at which the maximum appeared appears from the reversible counter 8, the amplitude of which differs 1 from the amplitude of the minimum preceding it by a predetermined value. In register 11 ^, the code of the level number at which the minimum appeared appears, is rewritten from the reversible counter 8, the amplitude of which differs from the amplitude of the preceding maximum by a specified amount. The code recorded in register 11η is decoded by 12 _{and a} unit is written into the corresponding maximum counter of memory block 13, and by register code 11 ιχ through decoder 12 is recorded one is set into the corresponding minimum of counter of memory block 13.

Since the disturbance causes a false extremal pair, in the analyzer the code is rewritten from the reversing counter 8 into the corresponding register 11 and the unit is written to the corresponding counter of the memory block 13 spaced apart in time.

For example, when a maximum appears, the first pulse from the output of the OR element 3η sets trigger 4 to one. The pulse from a single pulse output of the trigger 4 is fed to the element And 10η. With permission from scheme 9, this impulse comes through an AND 10η element and is fed to the control input of the 1C register, to the pulse input of the decoder 12ιχ and to the installation input of the register 11 This will overwrite the code of the level number on which the maximum appeared in register 11η; writing the unit to the corresponding minimum counter of memory block 13 using the code recorded in register 11 (^ (this code was recorded in register 11 о_ in the previous analyzer cycle, when a minimum appeared, whose amplitude differed from the amplitude of the preceding maximum by a specified amount), and resetting register 11 to zero, and writing the unit to the maximum counter for the code currently recorded

5 to register 11, will occur on the next analyzer operation cycle.

With an increase in the input signal, the elements of comparison 1 are triggered, from the outputs of the odd formers 2

o through the OR element pulses arrive at the zero input of the trigger 4 and through the delay element 6 o. to the summation inputs of the reversible counters 7 and 8. The first impulse received on

5 zero input trigger 4, does not change its state.

In the reverse counter 8, a code of the number of the current level is formed. In the reverse counter 7 is formed

: 0 code of the difference of the amplitudes of neighboring extrema.

When the input signal decreases (maximum at the point "4"), pulses from the output of the element begin to arrive

5 OR 3η The first pulse of this sequence sets trigger 4 to one state. The impulse from the output of trigger 4 goes through an AND 10η element, to which permission is applied from circuit 9, to the control input of the register 11η, the pulse input of the decoder 12 ^ and the installation input of the register 1 1 At the same time, the code of the level number is written to the register 11 _l

₅ which has a maximum, from the reversible counter 8, but there will be no writing of the unit to the memory block 13, since the register 11 ιχ is at zero. Pulse from trigger output 4 through

o The element OR 5 also resets the reversible counter 7 to zero.

I

After a time, pulses begin to arrive through the delay element 6 η at the inputs # of the subtraction of the reverse

e ’l

counters 7 and 8. At the subsequent minimum (point "5") the first pulse from the output of the element OR 3¾ sets to zero the trigger 4: From the zero pulse output of the trigger 4 they receive ³ pulses to the input of the element And 10 ^. So about how the difference of the amplitudes of a given minimum and the previous maximum does not exceed the specified one, then the signal from the output.

⁵ pulses through the element And 10 ^, and the code of this minimum will not be recorded in register 11 (y, and in the course of register 1 I _, no writing will be made to the memory block

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13. The impulse from the output of trigger 4 through the element OR 5 is reset to zero reversible counter 7 ·

Through time begins to flow through the element pulses ki zaderzh- 5 to the inputs of summation reversible counters 7 and 8. When the maximum value (point "6") pulse with a trigger output unit 4 passes through the AND gate 10 _{and the} (amplitude difference dan- * ⁰ Nogo maximum and the previous minimum exceeds a predetermined) and supplied to respective inputs of the register 11 and decoder ^ 12ιχ / overwrites this code with maximum ⁵ down counter 8 into register 11. ,, in which up to this point stored in the maximum code point _and "1".

At a subsequent minimum (point "7"), a pulse from zero output 20 of trigger 4 passes through an element AND 10ι ^ (the difference in amplitudes of extremes at points "6" and "7" exceeds the specified one) and goes to the corresponding inputs of registers and decoder 12 ^. 25 '

At the same time, the code of this minimum is rewritten from the reversible counter 8 to the register 1V), recorded using the register code 11 ·, one into the corresponding counter of the memory block maximum 30 13 (the counter contains information on the number of maxima at this level) and is reset to zero register 11.,. Further, the reversible counter 7 and is reset to zero. 35 after a time Tdod, pulses begin to flow through delay element 69 to the summation inputs of the reversible counters 7 and 8.

When the next maximum of 40 mum (point "5") appears, the pulse from the single output of flip-flop 4 does not pass through the element 10,, because there is no resolution from the circuit 9. At the same time, this code will not be written, 45 maximum in register 11. , and there will be no unit writing to memory block 13 using the minimum code at point "4", which is stored in register 11 (^. The impulse from the output of trigger 4 also resets 50 to zero the reversing counter 7 and after a while begin to arrive

pulses through the delay element 6 ·, to the subtraction inputs of reversible counters 7 and 8. 55

At the subsequent minimum (point "9"), the pulse from the zero output of trigger 4 passes through the element

And 10 ^ and this minimum code is overwritten in register 11 ^ instead of the minimum code at point "7" · the reversible counter 7 is also reset to zero and pulses start to flow through delay element 612 to the summing inputs of reversible counters 7 and 8 after time T ^ dd .

At the subsequent maximum (point "10"), the pulse from the single output of trigger 4 passes through the element 10 ·, as a result of which it is written into the register 11 ·, the code of this maximum, the unit is recorded by code, register 11 <^ in the corresponding minimum counter of the block memory 13. (data on the number of minima at this level is stored in this counter) and reset to zero register 11.,.

As a result of the operation of the analyzer, the memory block extremums of the random process under investigation (points "6", "9", "10") are allocated and recorded and false extremes are not recorded (points "4", "5", "7", "8" ) that are caused by interference.

The positive effect of the introduction of the present invention is to increase the noise immunity. and accuracy of analysis of statistical analyzers of random processes.

Claims (1)

Claim Statistical analyzer containing a group of comparison elements, the first inputs of which are combined and are the information input of the analyzer, the second input of each comparison element is the corresponding control input of the analyzer, a group of pulse shapers, the output of each comparison element of the group is connected to the inputs of two pulse shapers of the group the groups are connected respectively to the inputs of the first element OR, and the outputs of the odd group pulse generators are connected respectively, to the first input of the second OR gate, the output of the first OR gate is connected to one input of the flip-flop and through a first delay element. - with the subtractive input of the first reversible counter, the output of the second element OR is connected to another input of the trigger, and through the second ele11 Delay ment with a summing input of the first reversible counter, the bit outputs of which are connected to the inputs of the first storage register, respectively, the bit outputs of which are connected to the information inputs of the first decoder, respectively, the outputs of which are connected respectively to the inputs of the first group of the memory block, characterized in that the reliability of the analysis by eliminating false pairs of extrema, it contains the second decoder, the second memory register, the second reversible counter, two ele cient And, the digital comparator circuit and a further OR member, the inputs of the additional OR gate connected respectively with the output of the flip-flop and the first inputs of respective AND gates, the output of additional 'OR element connected to the mounting input of the second down counter ²⁵ kotoro- subtracting input connected to the output of the first delay element, the summing input is connected to the output of the second delay element, and the bit outputs of the second reversible counter are connected to the inputs of the first group of the digital circuit compared respectively, the output is 913394 12 The swarm is connected to the second inputs of the elements And, the output of the first element And is connected to the control input of the first storage register, with the control input of the second decoder and the installation input of the second storage register, the output of the second element And is connected to the control input of the second storage register, 10 with a control input ^ the first decoder of the torus and the installation input of the first memory register, the bit inputs of the second memory register are connected to the bit outputs of the first reversible counter, respectively o, the bit outputs of the second memory register are connected to the information inputs of the second decoder, respectively, the outputs of which are connected respectively to the inputs of the second group of the memory block, the second group of inputs of the digital comparison circuit are additional inputs of the analyzer.