SU888134A1 - Device for determining minimum sections of graph - Google Patents

Description

(54) DEVICE FOR DETERMINING MINIMUM GRAPH SECTIONS

Claims (2)

The device relates to computer technology and can be used to determine cross sections of various dimensions in the study of the reliability of systems described by graphs. A device for determining the connectivity characteristics of the graph p} is known, containing the element AND, memorizing the triggers of the vertices and branches, controlled by the key schemes of the graph displaying scheme. In the known device, a reliability assessment is carried out on the minimum number of branches separating the paths between a pair of nodes, which limits its use. Closest to this technical solution is a device for selecting a communication network 2, comprising a control unit, a network setting unit, a switch, a logic unit, triggers, registers, comparison units, counters. The prototype does not allow determining the number of minimal sections of a graph of each dimension. The aim of the invention is to expand the functionality of the device by taking into account the number of minimum sections by a custom size. The goal is achieved by adding the first and second blocks of the graph topology, the second distributor, two encoders, the OR element, the rpjmna AND elements, the trigger group, two groups of the OR elements, shift registers and a control unit, the i-th (, 2, N-1 output of the first distributor is connected to the -1-th input of the first group of the first graph topology shaping unit, the th input of the second group of which is connected to the -j output of the switch and to the i-th input of the first 3 encoder (, 1 1, 2,..,, N-1), the K-th output of which is connected to the first input of the element And group, the second input of which is connected to the K-output of the second encoder (K 1,2, .. N-2 /, the i-th input of which is connected to the output of the 1-st element OR of the first group, the code of the 1-th element of the AND group is connected to the | -th input of the OR element, the output of which is connected to the input the control unit and the first output of the shift register, the first input of which is connected to the first output of the control unit and the input of the switch, the L-th output of which is connected to the -l-TbiM input m of the first group of the second unit of the graph topology generator (, 2, ..., M-0, the K-th input of the second group of which is connected to the switch -f + 1-MU output of the switch (1 1.2, ... whose input is connected to the first inputs of group triggers, the output of that trigger is connected to the j -th input of the second distributor group (, 2 ,. ,, / I), the output of which is connected to the second input of the shift register, the input of the Y-th group meter is connected to the output of the shift register (and 1,. M-N + l), the i-th input of the j-th group of the first block The formation of the topology of the graph is connected to the 1st input J of the second element OR of the second group, the output of which is connected to the second input of the nth group trigger. (, 2, .. ,, N-1, 5 1,2,,.., The input of the first distributor is connected to the second output of the control unit, the third output of which is connected to the input of the second distributor, CI-th output of the K-th group of the second the unit for forming the topology of the graph is connected to the t input of the Kth element OR of the first group (1 1,2, ... N-2,, 2, ... Nlk}. The control unit contains a clock pulse generator, two triggers, four elements And, a counter and a decoder, and the output of the clock pulse generator is connected to the first inputs of the elements And, the outputs of the first, second and third elements And are the first, second and third outputs of the block, the output of the fourth element I are connected to the first counter input, the outputs of which are connected to the corresponding decoder terminals, the first output of which is connected to the first 4 input of the first trigger and the second input of the counter, the third input connected with the output of the first element And, the second input of which is connected to the second inputs of the second and fourth elements And and the output of the second flip-flop, the first input of which is the input of the block the second input of the second flip-flop connecting n with the second input of the third element And, the second output of the decoder and the second input of the first trigger, the output of which is connected to the third inputs of the second and third elements I. The first block forming the topology of the graph contains N-1 group of elements And that (l, 2, ..., Nl} groups are combined and are the 1st input of the first group of the block, the second inputs of the AND elements of the I -th group are combined and are the 1st input of the second group of the block, the output of the -th element f-one (j 1, 2, ... The / I) group is the 1st output of the block i-group. The second block forming the topology of the graph contains N-2 groups of elements AND, the first inputs of all elements AND - {- that (i 1, 2, ...,) groups are combined and are the i -th input of the first group of the block, the second inputs j of the AND elements of all the groups are combined and the high-voltage input of the second group of the block, the output of the 1st element of the AND -th group is;) -THE OUTPUT (j 1, 2,..., N-1 - 1) 4 - that group block. FIG. 1 shows a diagram of the device; in fig. 2 is a diagram of the first block forming the topology; in fig. 3 is a control block diagram; in fig. 4 is a diagram of a second topology generation unit. The device contains the distributors 1,2, the control unit 3 - the switch 4, the formation units of the topology of the graph 5 and 6, the counters 7 and 8, the triggers, the shift register 10, the counters 1C-11dd | di elements OR ZG% The direct unit of the formation of the topology contains the elements And 15 -15 ,, -l- 6M J7 -17 / w,. The control unit contains a clock pulse generator 19, elements AND 20-23, triggers 24, 25, counter 26, a decoder 27. The second unit of formation of the topology contains elements AND: ..,, SC. In the operation of the device, there are two more steps: the step of setting the graph graph and the step of calculating the number of minimal sections of the same dimension. Consider the stage of setting the structures of the graph. The basis for specifying a graph in a device is a graph with & M edges, in which everything is aeimean-wise. The structure of the graph on the block spr | roo ne topology 5 under rOT & sHtHsaeeTCR of the circuit of the operation of elements and the first line (the line corresponds to a certain vertex) KOTOpiae correspond to edges that are identical and always valid (all elements and in the line of block 5 as many as the edges in the graph). In the topology block in each line, the chain of operation of the elements AND of those verines that the given (consistent with the line) the non-funds means are connected to are prepared. Pervyyokyok 6 corresponds to the first higher one, having built the floor of the second in- erry th, ... the last line is the N-2nd faithfulNon of the graph. At the same time, the first AND line of the first line corresponds to the second vertex, 3JleMeHT - the third, ..., ate e-ny -N-1. Similarly, the first (left) element of the second row corresponds to the third vertex, the second to the fourth j ..., after it - the N-f-th verse of the graph. For the remaining lines of the block of the formation of the ishology 6, the designation of the elements AND in a manner described above. At the stage of calculating the number of minimum sections, the device operates under the action of pulses coming from control unit 3. The first pulse from the generator as well as the pulses 19 turns on the first output of the control unit. The signal from this output causes the triggers 9l -9dd and reads the information from register 10 to zero. At the same time, C, arriving at the input of switch 4, excites its first and second outputs. The signals from the switch outputs go to the topology shaping units 5, 6 and the encoder 8. The encoder 8, if there is a signal on any two inputs, excites the first output, on any three - the second, ..., on the N-1-o inputs - potential on N -2-bom output. If the numbers of the excited outputs of the switch correspond to the vertices directly connected to each other, then through block 6 the number of inputs of the encoder 7 will be excited by one less than the outputs of switch 4. The encoder 7, if one of its inputs is excited, generates a signal at output 1, two inputs at output 2, ..., if all N-2 inputs are excited - a signal at the N-2 output. Thus, if the first and second vertices of the graph are interconnected, the like outputs of the encoders 7 and 8 will be excited, then the signal will go to AND 15. And then to OR OR 14.; From the OR 14 element, the signal will be fed to the input of the control unit 3 and will write one to the zero bit of the register 10. If there is a signal at the control unit input, the next fvj-l pulses will be fed to the second output, the next DL pulses - to the third input and after passing K 1 and the aircraft and the pulleys will again excite the code 1 of the control unit, otherwise (if there is no signal at input 2) the second impulse will again excite the first output and force switch 4 to the next position. The pulses from the output 2 of the N-J control unit, going to the input of the distributor 1, alternate 1, 2, 3, ..., N-1-BbBi outputs in turn. Since the outputs 1 and 2 of switch 4 are excited, when the signal is sent to the second distributor code, the signal is removed from those AND elements of the first row, the response circuits of which are prepared by specifying the graph structure will be similarly when the signal is sent to the second distributor output. From the elements and rows of the topology shaping unit 5, through the elements of the ShZh 13, the signals arrive at the single inputs of the corresponding triggers and translate them into a single state. If the trigger chains of the same-name elements AND the two rows of the topology shaping unit 5 are prepared, the corresponding trigger will first go to one state and then return to zero. The next AL pulses arrive at the output 3 of the control unit and then to the input O of the distributor 2. The distributor 2 polls the triggers -9 when pulses arrive at its input and, if there is a single trigger state, generates a shift pulse into the parallel register 10. Thus, how many triggers be in the unit state, until such a bit the unit in the parallel register will be shifted (to the left) 10. The next momentum will go to the first output of the control unit and from it to the input of the S 9 flip-flop trigger 0, the input of the switch 4, which, going to the next position, will give signals to the outputs 1 and 3. With the arrival of the third pulse to the input of the switch 4, the outputs 1 and 4 are excited, then 1 and 5, 1 and 6 ... 1 and then 2 and 3, 2 and 4, ... 2 nN-i, 3H4, ..., M-2 and NI, in the lastest 1,2 and 3; 1,2 and 4; ... etc. to 1,2,3, ..., N -1. After processing the cycle with the excited 1,2,3, ..., N-1 outputs of switch 4, the switch will accept the initial state, and the device will finish counting the minimum cross sections of the graph. The counters are shown as the number of minimum cross sections, the difference in the cross section coincides with the number counter. The device makes it possible to simplify the process of isolating minimal sections of a graph in the study of the reliability of systems. Claim 1. Device for determining minimum sections of a graph containing a group of counters, a first distributor and a switch, characterized in that, in order to expand its functionality by taking into account the number of minimum sections of each dimension, the first and second blocks are additionally inserted into it the formation of the topology of the graph is the second distributor, the two encoder element OR, the group of elements AND, the group of triggers, two groups of elements OR, the shift registers and the control unit, with the 1st (, 2, ... NI) output of the first distribution The driver is connected to the first input of the first group of the graph topology formation unit, the i input of the second group of which is connected to the lth output of the switch and to the i input of the first encoder (l 1, 2. ./-1 ), The K-th output of which is connected to the first input of the K-th element of the AND group, the second input of which is connected to the C-th you- the second encoder (K 1, 2,... jN-2), the i -th input of which is connected to the output of the i -th element OR of the first group, the output of the -1th-element AND group is connected to the 1st input of the OR element, output which is connected to the input of the control unit and the first output of the shift register, the first input of which is connected to the first output of the control unit and the input of the switch, the i -th output of which is connected to the i -th input of the first group of the second unit of the graph topology (1,2, .. ,, N-1), the K-th input of the second group of which is connected to the output of the switch, 2, ..., N-2), input to The op is connected to the first inputs of the group triggers, the output of the j of the trigger is connected to the j of the group of the second distributor (1,2, ..., the output of which is connected to the second input of the shift register, the input of the group's I counter is connected with VI + 1st output of the shift register (and 1, ..., MN +1, {-th output of the -j -th group of the first block for forming the topology of the graph is connected to the i-th input of that OR element of the second group, the output of which is connected to the second input of the group trigger (1,2,. ., N-1 g} 1,2, ..., M) the input of the first distributor is connected to the second control unit, the third output of which is connected to the input of the second distributor, the M-th output of the K-th group of the second block forming the topologies of the graph is connected to VV to the first input of the K-th element OR of the first group (K 1,2, ..., N-2,, 2, ..., N1-K). 2. The device of claim 1, wherein the control unit contains a clock pulse generator, two triggers, four elements, and a counter and a decoder, the output of the clock generator connected to the first inputs of the elements I, the outputs of the first, the second and third elements And are respectively the first, second and third outputs of the block, the output of the fourth element And is connected to the first input of the counter, the outputs of which are connected to the corresponding inputs of the decoder, the first output of which is connected to the first input of the first three Gera and the second input of the counter, the third input of which is connected to the output of the first element And, the second input of which is connected to the second inputs of the second and fourth elements And the output of the second 14 of the ygger, the first input of which is the input of the block, the second input of the second trigger connected to the second the input of the third element I, the second output of the decoder, and the second input of the first trigger, the output of which is connected to the third inputs of the second and third E elements I. 3. The device according to claim,, distinguished by the fact that the first block forming the topology of the graph with q laughs NI group of elements And, at 4. 10 than the first inputs of elements AND -1 –th (i 1, 2N-I groups are combined and are the fifth input of the first group of the block, the second inputs of elements AND of the i -th group are combined and - the i-th input of the second group of the block; the output of the j-th element of the AND-i-th (-} 1,2, ..., M) group is the - th output of the -th group of the block. 4. The device according to claim 1, characterized in that the second block of the formation of the topology of the graph contains 1 -2 groups of elements AND, the first inputs of all elements AND i -th (-1 1, 2,.,. H-2 / group combined and are the first input of the first group of the block, the second inputs of the lth elements AND of all groups are combined and are the j -th input of the second group of the block, the output of the -j -th element And the j -th group is the -th output (j 1,2, ..., N -1- a) i groups of the block Sources of information taken into account during the examination 1. USSR author's certificate No. 468244, class G 06 F 15/36, 1971. 2. USSR author's certificate for application No. 2414862 / 18-24, cl. G 06 F 15/36, 1976 (prototype). // T / t /. g if From 4 / ry / - / y y. From K0f (fff ffff7fffrff d 11 St iff GTK GZ 9m il / iff-ff fwi.3 15 T / j