SU1596344A1 - Device for solving problems on graphs - Google Patents

Abstract

The invention relates to computing and can be used to study paths in graphs. The aim of the invention is to improve the speed of the device when solving the problem of determining the shortest path in a graph with weighted vertices. The device contains a block 46 specifying the adjacency matrix, block 47 determining the shortest route, register 48, switch 49 adjacent vertices, multi-channel accumulating block 50 for selecting the minimum amount, inputs 51 specifying the device vertex weights, inputs 52 specifying the initial vertex of the device, outputs 53 signs of arcs belonging to the set the shortest path arcs of the device, the clock inputs 54, 55 of the device, the switch 56 of the incident arcs and the inputs 57 specify the final vertex of the device graph. Before starting, the register 48 is zeroed, block 46 is entered into the topology of the graph, the vertex weights are entered into the channels of the block 50, the same codes are fed to the inputs 51. One of the bits of the register 48 corresponding to the number of the initial vertex of the path, set on input 52 to one state. The inputs 54, 55 are alternately supplied with clock pulses of the logical unit level. In this case, the block 47 forms at the outputs 53 of the device signs of belonging of arcs to the set of arcs of the shortest path. 5 il.

Description

us. S The invention relates to computing and can be used to examine paths in graphs. The whole of the invention is to increase the speed of the device when solving the task of determining the shortest path in a graph with weighted vertices. Figure 1 shows the functional scheme of the device; 2 is a functional diagram of a control unit; FIG. 3 shows an example of modeling a graph; in FIG. 4, stages; determine the best way in the graph; Fig. 5 shows a generalized structural arrangement. The device ,, (Fig. 1) contains a shift register 1, a reverse shift register 2, an adder 3, a control unit 4, a trigger 5, a group of triggers 6 (1) -6 (B), elements 7 and 8, two groups of elements And 9 (1) -9 (B) and 10 (1) - / 10 (B), elements OR 11-13, element. AND-IPI 14, element EXCLUSIVE OR 15 element OR-NOT 16, group of elements OR-NOT 17 (1) -17 (В), keys 18 and 19, information inputs 20 (1) -20 (В), informational output 21, information inputs 22 (1) -22 (В) and indicator outputs 23 (1) -23 (B), where B is the number of vertices in the graph. The control unit 4 (FIG. 2) comprises a pulse generator 24, a pulse distributor 25, a single pulse generator 26, which has 27 29, tons of iggers 30-33, a delay element 34, AND 35-39 elements, OR elements 40-42, an OR element -NE 43, elements 1 NOT 44 and 45. In FIG. 5, an adjacency matrix setting unit 46, a shortest route determination unit 47, a register 48, an adjacent vertex switch 49, a multi-channel minimum sum accumulating unit 50, device 51 vertex weights inputs , inputs 52 specify the initial vertex of the device, outputs 53 signs of The arrays of multiple arcs are brief; your device’s path, the lactic inputs 54 and 55 of the device, the switch 56 of incident arcs, and the inputs 57 define the final vertex of the device graph, .. Figure 4a shows an example of a graph with weighted vertices whose weights are indicated inside the vertex symbol - tires. The initial vertex is denoted by the letter H, and the final - by the letter K. The algorithm for finding the shortest path; in the column of FIG. 4, the following is summarized. Mark all vertices associated with the initial vertex. The label of the vertices is performed by a square inside the vertex of the graph. The weight of all marked vertices 8, 7, and 2 adds the initial node weight equal to one. The resulting sum is stored in the marked vertices 9, 8 and 3. After these operations complete the first step of the calculations, we get the graph shown in fia of Fig. 46. Further calculations are performed from all previously labeled vertices. Mark all vertices of the graph connected by arcs with labeled vertices at the previous step of the graph. In the second step of the calculation, a final vertex and a vertex with a weight of 4 are to be labeled. Select the minimum sum of weights from all previously labeled vertices associated with directed arcs to the marked Kish ees 4. The vertex with a weight of 4 is associated with: labeled vertices, in which after The first step of the calculation is the sum of the weights equal to 8 and 3 (figb). The minimum sum of 8 and 3 is equal to 3. This minimal sum of 3 is summed up with the weight of vertex 4 and is stored in it as a new weight 4. + 3 7 (figv). Similarly, for the final vertex, select the minimum sum of two labeled vertices 9 and 8. The minimum sum, equal to 8, from the number of all labeled vertices in the first step, is summed with the zero weight of the final vertex and is remembered in it. After the second step of the BEI, we have the graph shown in figv. The arc connecting the final vertex with the vertex weighing 4 was not taken into account at the second calculation step, since the vertex weighing 4 before the beginning of the second computation step was not labeled. The calculations in the third step of the calculations are performed for all the cardi ng nodes. Now, when choosing the minimum sum of weights arriving at the final node of the graph, it is necessary to take into account all the vertices of the graph associated with directed arcs with the final vertex. So, at the third step of the calculations, the sum vertex receives the sum veCQg. -From vertices 9, 8 and 7 ( Figd). The minimum sum of 9, 8 and 7, equal to 7, is summed with the zero weight of the final vertex and is stored at the final vertex instead of the previous value 8, which was formed in the previous step. This ends the computation because the state of all labeled vertices does not change.

Thus, the weight 7 of the final vertex of the graph after the completion of the calculations is equal to the length of the shortest path. The shortest path configuration is determined from the graph of FIG. 4d, starting at the end node, along the arc along which the minimum sum of weights is equal to 7. This arc connects the final vertex with vertex 7 in FIG. 4d. Vertex 7 is connected to vertex 3 by the shortest path arc, which is connected by an arc to the initial vertex N. Therefore, the shortest path on the initial graph (Fig. 4a) goes through (3, 2, 4, O vertices and is marked by double arcs.

The pulse generator 24 of the control unit 4 (FIG. 2) generates a sequence of clock pulses of frequency f, of which the distributor 25 pulses form n sequences of frequency pulses f / n shifted each other relative to each other for time 1 / f, where n is the number of bits representing the weight of a graph node,

. In the mode of inputting the weight of the graph nodes into the shift register 1 by the switch 28 (performed, for example, in a two-position switch) of the control unit 4 connect the output of the generator 26 of single pulses to the installation input to the trigger unit 30. With the help of the new switch 27 (performed For example, in the form of a key switch) of the control unit 4, a binary code of the weight of the graph node is set. The switch 27 connects in unit bits of the binary code of the node weight the corresponding outputs of the distributor 25 pulses to the inputs of the element OR 40, at the output of which a sequential binary code of the node weight is formed. For example, if the weight of the node is equal to 101, then the outputs of the first and third the bits of the distributor 25 pulses are connected by the switch 27 to the inputs of the element,

Serial binary input. The Node weight code in the p-bit shift register 1 is made after the switch 29 (made, for example, in the form of a push-button switch) applies a single signal from the output of the HE element 44 to the start input of the pulse generator 26, which extracts from the sequence of pulses the output of the element 35, acting thin at a frequency f / 2n, is a single impulse that, via switch 28, sets trigger 30 to the unit state for time n / f.

The trigger 31 of the sequence of pulses of the n-th bit of the distributor of 25 pulses forms two sequences of pulses.

These two sequences of pulses alternating with the frequency f / 2n on the forward and inverse outputs of the trigger 31 define two time cycles of operation of the device. We assume that the sequence of pulses at the forward output of the trigger 31 determines the first cycle, and at the inverse output the second cycle. Then the trigger 30, which is set to a single state by a single pulse at the end of the second cycle, will be in a single state during the first cycle, at the end of which it is set to the zero state by a pulse of the nth times of the distributor 25 pulses.

A single direct output signal of trigger 30, access to the control input of the 1 shift register, provides a record, starting with the low-order bit,

5 consecutive binary code of the weight of the node of the graph coming from the code of the element OR 40 of the control unit 4 to the data input of the shift register 1. Writing binary code to register

0 1 shift is carried out under the action of the clock pulses of the generator 24 pulses of the control unit 4 received at the synchronization input of the shift register 1. After writing the binary

5, the graph node weight code is stored dynamically in the shift register 1 due to its circulation from the output of the shift register 1 to its information Q input under the action of the clock pulses of the pulse generator 24 of the control unit 4.

In the weighing input mode, the triggers 6 (1) -6 (B) are in zero state55

. in which they are installed on the inverse zero input of a single pulse of the generator 26 of single pulses, coming through the element 45 of the control unit 4. The trigger 5 is set to the zero state by pulses acting on the output of the generator 26 of single pulses of the control unit 4. The trigger 32 of the control unit 4 is set to the zero state by pulses of the first discharge of the distributor 25 pulses. The pulse sequence of the output element AND 35, acting through the element AND 38, opened by the inverse output of the trigger 32, sets the trigger 33 to the zero state. After writing in the first cycle of the binary code of the node weight in the shift register 1, this code in the second cycle under the action of the clock pulses of the generator 24 pulses of the control unit 4 is written, starting with the lower order, through the adder 4 into the reverse shift register 2. In the simulation mode, the switch 28 of the control unit 4 connects the output of the generator 26 single pulses to a single input of the trigger 33. The starting node of the graph is set with a key 18 by connecting the output of the generator 26 of single pulses of the control unit 4 to the input of the element 11. The end node of the graph is set with a key 19, which connects the inverted output of the trigger 33 of the control unit 4 to one of the inputs of the element OR 12. The device is started up by the switch 29 of the control unit 4, through which the single impulse generator 26 starts up cos p6dshot NOT element output signal 44. The output pulse generator 26 single-pulse control unit 4 receives through the switch 28 on the unit input latch 33 and sets it in a single state, and after. the key 18 of the module containing the initial node of the graph sets the trigger 5 of this module to one. The trigger 5 of the initial node of the graph in the single state removes the blocking of the first and second groups of inputs of the I-ШШ 14 element, blocking its third group of inputs. During the first cycle of the device operation, under the action of the unit signal of the direct output of the trigger 31 and the sequence of clock pulses of the generator 24 pulses of the control unit 4 from the reverse shift register 2, the binary code of the weight of the initial node of the graph is shifted. starting with the older bit. This binary code, shifted from the reverse shift register 2 by the higher bits, is again written to the reverse shift register 2 by the write input during the left shift, as well as through the AND-OR element 14 enters the information output 21 of the module containing the initial node of the graph, and further, according to the topology of the graph for the information inputs 20 (1) -20 (B) of other modules of the building structure. We will further assume that the modules in which the trigger 5 is set to one state are in the excited state, and the modules containing the trigger 5 are in the zero state are in the unexcited state. In the unexcited state, the modules produce at the information output 21 a sequence of double pulses generated at the output of the OR element 42 of the control unit 4 from sequences of pulses that are produced at the outputs of the AND elements 35 and 37 of the control unit 4. At the output of the element And 35 of the control unit 4, a sequence of pulses of the nth discharge of the pulse distributor 25 is generated, which is active during the second cycle of operation of the device with a single signal at the inverse output of the trigger 31 of the control unit 4. neither At the output of the element 37, a sequence of pulses of the first discharge of the distributor 25 of pulses acts during the first cycle of operation of the device with a single signal at the forward output of the trigger 31 of the control unit 4. Thus, at the output of the LII element 42 of the control unit 4, a sequence of double pulses is generated, acting in the first discharge of the first cycle and in the nth discharge of the second device operation. The pulse sequence of the output of the element OR 42 of the control unit 4 is transmitted through the elements AND-OR 14 to the information outputs 21 of all unexcited modules of the modulating structure, in which the trigger 5 is in the zero state. After the control unit 33 of the control unit 4 is set to one state, a sequence of n-th digits of the second cycle starts through the element I 39 and is delayed by the delay element 34 for the duration of the clock pulse generator 24 of the control unit 4. The first impulse of the sequence of the output of the AND 39 control unit 4 sets the triggers 6 (1) -6 (B) in all modules of the modeling structure into single states at which the blocking of the elements OR-NOT 17 (1) -17 is released ( B), since zero signals are set at the inverse outputs of the 6 (1) -6 (B) flip-flops. In addition, in the simulation mode, when the trigger 33 of the control unit 4 is set to one, the element OR-HE 43 of the control unit 4 is locked from the inverse output of the trigger 33. The control sequence of the second cycle from the inverted output of the trigger 31 the control unit 4 is inverted the element OR-NE 43 of the control unit 4 and in the form of a control of the sequence of the first cycle is fed to the input of the elements AND 7 of all modules of the modeling structure. In the first cycle of operation of the device in the modules of the modeling structure, the information inputs of which are 20 (1) -20 (B) receive consecutive binary codes, starting with the highest bit, the selection of the smallest binary code is performed. This is done as follows. If at least one binary code contains zero in the high-order bit, then the output of the corresponding element OR-H 17 forms a single signal that passes through the element AND 7 to all elements AND 10 (1) -10 (B) and resets to zero nor triggers 6 (1) -b (B) c. those channels in which, on the information inputs 20 (1) -20 (V), a single signal acts in the higher order. Further analysis of binary codes at inputs 20 (1) -20 (B) is performed similarly — bitwise from the highest bit to the lowest bit — during the time of the first cycle, which is n cycles. After the end of the first cycle, the trigger of the 6th (K) channel, in which the smallest binary code (K 1, ..., B) was in the single state, appears. In the second cycle of operation of the device, the modules of the modeling structure that are in the excited state, vyod 1 from the reversing register 2 of the shift through the AND-OR 14 elements to the information output 2, the serial binary weight code, starting with the low-order bit, i.e. younger bits ahead. The issuance of a binary code from the reversing shift register 2 is carried out under the action of the clock pulses of the pulse generator 24 and the control sequence of the second cycle operating at the inverse output of the trigger 31 of the control unit 4. The smallest consecutive binary code acting, for example, in the Kth channel, comes in lower bits ahead through the elements SHSh-NOT 17 (K), OR 13 and OR-NOT 16 to the input, sequentially: GO of the adder 3, to the other. the input of which, under the action of pulses of the pulses of the generator 24 of the pulses of the control unit 4, shifts from the output of the shift register 1 the serial binary code of the weight of the node of this module modulates its structure. SUMATOR 3 performs sequentially in time, starting with the least significant bit, the summation of the binary code of the shift register 1 and the smallest binary code received at the information input 20 (k). The result of the summing from the output of the adder 3 is recorded, starting with the least significant bit, into the reversing shift register 2 under the action of the clock pulses of the pulse generator 24 and the control sequence of the second cycle formed at the inverse output of the trigger 31 of the control unit 4. Moreover, the connection of one of the inputs of the element OR NOT 16 to the direct input of the flip-flop 31 of the control unit 4 ensures that codes are transmitted through this element only during the second cycle of operation of the device. During the transmission of the smallest binary code from the information input 20 (K) through the elements of the CRPD-NOT 17. (C) and OR 13 in the last nth bit of the second cycle, the trigger 5 of this module is set to one, i.e. . transfer of excitation from one MODULE simulating the structure. to another. Indeed, in the nth. the (highest) bit of the smallest code contains zero, which is transformed when transmitted through an OR-NOT 17 (k) element into a single signal that sets: AND 8 and OR t.1, 15 trigger 5 elements of this module into the -unit state the In the future, the device works in a similar way. The sequential binary code of the weight of the initial node of the graph transfers the excitation of the computational process to other modules of the modeling structure, which are selected in the first cycle. the smallest dvoggny code from all the codes acting on the information inputs 20 (1) -20 (B) 5 a in the second cycle adds to the smallest binary code the weight of the node of this module by the model structure. In the first cycle, the unexcited modules of the modeling structure produce a maximal binary in the first cycle: the code is a unit in the first (senior) bit, coming from the output of the AND 37 elements of the control unit 4 through the control unit 42 of the control unit 4 and the AND-14 element to the informational output 21 of this module. Therefore, the maximum binary codes lagging behind the non-emitted modules of the modeling structure on the information inputs 20 (1) -20 (B) of the module, do not affect the choice of the smallest binary code from all the codes received from the excited modules. If all information inputs 20 (1) -20 (B) of this module are supplied with maximum binary codes from unimplemented other modules, then this module remains in an unexcited state, since the pulse of the n-th bit of the second cycle from the output of the And 35 element by acting through the item. OR 42 of the control unit 4 and the element. AND-OR 14 of the unmodified module, passes through the input 20 (k) of this module to the output of element 1-ШИ-НЕ 17 (К) in the form of a zero signal, which blocks the element And 8 and prevents the installation of the trigger 5 of this module in one state. At this time, the element 16 is blocked by a pulse of the n-th bit of the second cycle, coming from the output of the element And 35 of the control unit 4. In the process of modeling, trigger 33 of control unit 4 saves a single state, since in the course of calculations sequential binary codes shifted by lower bits from the output of the reverse register 2 shifts and binary codes acting at the output of totalizer 3 are different. Therefore, at the outputs of the EXCLUSIVE RSHI elements of the 15 modules, single signals are generated, which are fed to the inputs of the EFI element 41 of the control unit 4 and through the AND 36 element opened in the second cycle by the inverse output signal of the trigger 31, the trigger 32 is set to one until the moment of the pulse n th digit of the second cycle at the output of the element 35. As a result, the element 38 at the time of the action of the pulse of the nth digit of the second cycle is closed by the zero signal of the inverse output of the trigger 32, and the trigger 33 saves the unit oh state. The calculation process in the modeling structure ends when the excitation process spreads from the initial node of the graph to all its other nodes. In this case, dynamic equilibrium occurs in the modeling structure. Each module of the modulating structure at the P-th calculation step allocates the same smallest binary code that was allocated at the previous (P-1) -th calculation step by the inputs 20 (1) 20 (c). In each module of the modeling structure, the sum of the smallest binary code allocated by the inputs 20 (1) -20 (B), with the binary code of the node weight of this module shifted from the output of the shift register 1, at the Pth calculation step is equal to the sum allocated to the previous one (Р-О-th calculation step and stored in the reverse shift register 2. On the BbiKcie elements EXCLUSIVE OR 15 of all modules of the modeling structure acts during the second cycles zero signals, and the trigger 32 of the control unit 4 is set to the zero state by the first discharge pulse distribute 23 pulses. A pulse of the n-th bit, of the second cycle, acting at the output of the element 35, sets the element 33 through the element 38 to the zero state. The single signal generated at the inverse output of the trigger 33 of the control unit 4 passes through the key 19 into the module containing the final node of the graph. If in this module the smallest binary code acts on the T-th input and the trigger 6 (t) is in the unit state, then the unit signal from the output of the key 19 passes through the elements OR 12, and 9 (to ) on the indicator output 23 (t) and then goes to one of the indicators The input inputs 22 (1) 22 (c) are a forwarding module of the modeling structure. If in this module a smaller binary code acts on the Kth input and the trigger 6 (K) is in the unit state, then the single indication signal 23 (K) further spreads in moduli of the modeling structure from the end node of the graph to the initial one. the node along the shortest path, I will correspond to the smallest sum of the weights of the graph nodes. A binary code, proportional to the non-shortest path, is generated during the simulation in the reverse shift register 2 of the module containing the final node of the graph. After completing the calculations, the smallest sum of the graph weights between the start and end nodes is output during the second cycle under the action of the clock pulses of the pulse generator 24 of the control unit 4 from the reversing shift register 2 through the AND-OR 14 .. element to the information output 21 of the module containing the final node graph. Thus, in general, the operation of the device can be represented as follows (figure 5). Before starting, the register 48 is zeroed, the information about the topology of the graph is entered into the block 46 of the setting of the adjacency matrix, the weight codes of the vertices of the graph are entered into the channels of the block 50, the same codes are fed to the inputs 51. corresponds to the number of the initial vertex of the path, set at the entrance 52 in unit position. In this case, the switch 49 provides for its outputs a vertex composition. adjacent to the respondents, and the switch 56 to its (K, M) -th information input (K 1, ..., B; M 1,.,., B) the code received at its K th information input, if The Kth information input is connected and there is a resolution; to connect the Kth information input of the Mth information output, the weight of the path accumulated by the K channel of block 50 is transmitted to (K, M) th information output. sufficient to complete the specified operations, to the input 55 of the device

Claims (1)

impulse a level of logical one; In addition, each channel of block 50 adds the value of the first to the set of arcs of the shortest path of the device, characterized in that, in order to increase the speed with the values of each of the second, the terms (other than zero) selects the minimum value of the sum, compares it with previously accumulated and, if the latter is greater, fixes the current value of the sum and the number of the second term. Thus, the minimum of all paths to each vertex is selected from among all the peaks already reached and the arcs belonging to the shortest path are marked. After a time sufficient for these processes to end, to the input 54 of the device podkha the impulse level logical unit. In this case, the register 48 records (by OR) the information received at its information input, thereby including new vertices. Further, the operation of the device is repeated until block 50 records the absence of any changes (the value of the minimum amount in any of the channels or its position). At the same time, the shortest route determination unit 47 forms, at the device outputs 53, signs of arcs belonging to a set of shortest path arcs. The invention includes a device for solving problems on graphs, containing a block for specifying an adjacency matrix, a block for determining the shortest route, a register, a switch for adjacent vertices and a switch for incident arcs, the Kth bit of the information output of the register (K 1, ..., B, where B is the number of vertices in the graph) is connected to the K-th information input of the commutator of adjacent vertices and to the input of the K-th information direction of the switch the incident arcs, the output value (K, M) of the th element of the adjacency matrix setting block (M 1 ,. .., B) is connected to in Odam permitting the connection of the Kth information input to the Mth information output of the switch of adjacent vertices and the switch of incident arcs and to the input of the presence indicator (K, M) of the arc of the shortest route determination unit, the output of the attribute of belonging (K, M) and the shortest arc the route of which is the output of the attribute of the (K, M) th arc;: when the device determines the shortest path in the graph with weighted vertices, a multichannel accumulating block for selecting the minimum sum is entered into it, and the Mth information output The d switch of adjacent vertices is connected to the M-th bit of the information input of the register, the installation input of 1 K-th bit of which is the input of setting the initial vertex of the device graph, the input of setting the weight of the K-th peak of which is connected to the input of the first addend K- channel of a multi-channel accumulative block for selecting the minimum amount, the information output of the K-th channel of which is connected to the K-th information input of the switch for incident arcs, (K, M) -th information output of which is connected to the K-th input of the second Z2rfJ of the addendum of the Mth channel of the multichannel accumulation of its minimum amount selection block, the Kth output of the position of the minimum sum of the Mth channel of which is connected to the input of the sign of belonging (K, M) of the arc to the set of arcs of the shortest route of the block determining the shortest route, M The th input of the tasks of the final vertex of the route of which is the M th input of the task of the final vertex of the device graph, the first and second clock inputs of which are connected respectively to the input.:. the sign of the register and to the clock input of the multichannel accumulating block for selecting the minimum amount, the output of which does not change sign is connected to the polling input of the final vertex of the block determining the shortest route. . one n