SU1501021A1 - Function generator - Google Patents

Abstract

The invention relates to computing technology and is intended for use in control systems for flexible automated manufacturing processes, in specialized computing devices. The aim of the invention is to expand the class of tasks. To achieve this goal, a single-bit memory block, a decoder, a memory node block, a third switch, a third trigger, a fourth and fifth And elements, and a third counter are entered into the device. The additionally introduced elements allow realizing the functional transformation of a given number of continuous strictly monotonic functions by using reproducible functions recorded in the memory nodes of the block of local trends. Expansion of the class of solved problems is achieved with a slight increase in equipment and maintaining high accuracy-time characteristics. The conversion algorithm consists of two steps. At the first stage, the sweep of the function is carried out by an increased step in a certain average bit using local trends of this bit and the function is incremented by quanta. At the second stage, the sweep is carried out in small steps in the lower category. 1 il.

Description

The device relates to the field of computing technology and is intended for use in control systems of flexible automated manufacturing, technological processes, and in specialized computing devices.

The aim of the invention is to expand the class of tasks to be solved due to the possibility of converting a given number of continuous monotonic functions.

The drawing shows the functional diagram of the Converter.

The device contains a one-bit memory block 1, a decoder 2, a block of 3 memory nodes, switch 4, adder 5, switches b, 7, adder 8, registers 9, 10, comparison circuit 11, counter 12, trigger 1 3, element IL M 14, trigger 15, generator 16 pulses, elements AND 17 and 18, counter 19, register 20, delay elements 21-23, element AND 24, element OR 25, trigger 26, elements And 27 and 28, counter

l :)

3150

29, a device clock input 30, a device function input 31. The first adder 8 is made combinational, and the second 5 is accumulating.

In general, the method of transformation of continuously strictly monotonic functions will be written as follows:

L. (p + l) L, (p) +4 Sq, (p),

r + (

 "V

F (t

P + t

 , / (n),)% (tj ,,) + sign (g) -2

L / j-Ы) L (p + l) / 2

A-V

p + 1

stage 2.

J + a

+ L. (j + 1),

) F (t) sign (r) -2 where r 1 is for strictly monotonically increasing functions and g -1 for strictly monotonously decreasing functions. .

The initial values are L (, (o) nd (; and S (o) 4 о o, where L L is the final difference of the reciprocal function (t) on a uniform grid with a step. As the initial value of the function its value

F (t,).

The q-number of the bit, in which the sweep is performed with an increased step, is determined from the expression

 - logjC (L M X,)

jCflT

h

),

1 (2

. where d csr + 1, 4 are the finite differences of the first and second order of mutually inverse function Φ (t) on uniform grids, respectively, with steps 2 and 2-14 tf}. In practice, it suffices to check the condition in those grid nodes where function F ( t) has the greatest curvature.

Dp continuous strictly monotone functions as a rule, where

  - a whole with an excess.

The device works as follows.

In the initial state, register 9 and adder 5 recorded the binary code of the interval of the constant L (o), counters 12 and 19, triggers 13, 15, 26 are reset.

The first counting pulse from the input 30 of the device enters the counter 12,

increasing its content by 2

L

through the element OR 14 on the counting input of the trigger 15, peregacha it in the unit. Pass delay element 21, score 21

the first pulse resets the low-order (L - q) bits of the counter 19. The unit from the direct output of the flip-flop 13 arrives at the inputs of the And 17 and 18 elements. Element And 18 is opened by the signal 1 from the inverse of the flip-flop 13.

The function code comes from the input 31 of the device to the decoder 2 and switch Q. 4. The code from the output of the decoder 2 goes to the enable inputs - block 3 of the memory nodes and allows reading information from the j-ro node where the local trends of the j-th convertible function. In switch A, the code from input 31 controls the transfer of 5 local trends from the j-ro node of block 3 to the input of the adder.

The clock pulses of the generator 16 0 pulses, having passed the open element I 18, arrive at the counting input with the weight 2 of the counter 19, increasing its contents by. In addition, the clock pulses through the open signal 5 from the inverse output of the trigger 26 and the element 27 are fed to the counting input of the counter 29, increasing its content by 1. On the trailing edge of the clock pulse, the counting trigger 26 0 switches to 1. Read from

The j node of the next lacal trend q-ro bit is fed through switch 4 to the input of the adder 5. The next clock pulse is received through an open signal 1 from the direct output of the trigger 26 element I 28 to the clock input of the adder 5, in which the next interval of the constant 0 L (p + l) is calculated.

On the trailing edge of the current pulse, the trigger 26 changes its state to the opposite, with a 5-l recalculation of the clock pulses modulo 2.

The code from the output of adder 5 is fed through switch 6 to the input of the second term of adder 8, the Hd input CQ of the first addend which receives the code from the output of register 9. As a result of the addition operation, the binary code of argument t appears at the output of adder 8. In the comparison circuit 1 2, the code from the output of the adder 8 is compared with the code of the argument t, coming from the output of the counter 12.

If tp.j, then the output of the comparison circuit 11 is zero. In that

150102

In the case of register 10, the code from the output of the adder 8 is written. With a sweep with an increased step, register 9 records the code from the output of the adder 8 regardless of the comparison result.

Upon the appearance of the output of the unit comparison circuit 11, the trigger 13 switches to cinidine and zero from its inverse output closes the AND 24 th element, and in register 10 the same value of the sum of the constant q-ro intervals remains.

The transition to the second stage of the conversion, i.e. to deploy- 15 keke small steps. Clock pulses through an open signal from the direct output of the trigger 13 element And 17 are fed to the counting input with a weight of 2 counters 19. To the input of the first component, - the MOM adder 8 goes through switch 7, the code from the output of the register 10, and the input to the second component is shifted in the switch 6 on (A h) bits towards the lower ones, the code of the (p + 1) -th interval of the constancy of the q – ro bit. As a result of the addition in the adder 8

20

25

pulses, two OR elements, three AND elements, three delay elements, the clock input of the converter is connected to the first inputs of the first element {-shi, the first load element and the counting input of the first tip, the output of which is connected to the fifth input of the comparison circuit, the second input of which is connected to the output of the fifth adder and informational in the first and second register dyes, which are connected to the first and second informational outputs of the first switch, respectively, the output is connected to the input of the first adjacent first adder, the input to The output of the second switch which is lagged, the control inputs of the first and second switches are connected to the forward output of a trigger, the counting input connected to the output of the comparison circuit the inverse output of the first trigger I, to the second and third inputs of the second my second trigger output and the pulse generator's output are connected respectively;

its output appears argument code

tj, which is compared in the circuit 11 30 to the first input of the second element I, with the spin code of the counter 12.

compare ,, ,, -, -,

The code of the argument t О is written to register 10. At this time, the contents of counter 19 are recorded in register 20. Synchronization of the record in 5 registers 10 and 20 is effected by pulses from the output of the second element OR 25. The second stage of the conversion is carried out until , while the output of the circuit 11 is not in comparison with 40 with one. Then the trigger 13 switches to zero, switching in turn the trigger 15, the zero from the direct output of which closes the elements 17 and 18. At this, the calculation of the current 45 value of the continuous strictly monotonic function F (t) ends, its value is written to the register 20.

When the next counting pulse arrives at the input 30 of the device 50, the described computing process repeats.

Claims (1)

Invention Formula the second and third inputs of which are connected with direct outputs of the first and second triggers respectively, are connected to the counting inputs of the second and second counters of the first and second elements, respectively, and 2, where L is the width of the argument q is the number of the digit from which Ved with a sweep with an increased step, the second counter stroke is connected to the information input of the third register, the output of the second element AND connected via the second delay element by the first input of the second element OR connected by the output to the sync input of the second register, the output of the second The AND element is connected via a third delay element to the synchronization input of the first register and the first input of the third element AND, the second input of which is connected to the inverse output of the first trigger, the output of the third element H is connected to the second input of the second element OR, the output of the first element of the delay connect to the installation input to the lower arrays of the second counter, the direct output of the first trigger is connected to the second input of the first NTK element Functional converter containing two counters, two adders, two switches, a comparison circuit, three registers, two triggers, 1 generator 0 five pulses, two OR elements, three AND elements, three delay elements, the clock input of the converter is connected to the first inputs of the first {-SHE element, the first delay element and the counting input of the first counter, the output of which is connected to the first input of the comparison circuit, the second input of which is connected to the output of the first adder and information inputs of the first and second registers connected by the outputs respectively to the first and second information inputs of the first switch, the output of which is connected to the input of the first addend The first adder, the input of the second term of which is connected to the output of the second switch, the control of the first and second switch inputs are connected to the direct output of the first trigger, the counting input of which is connected to the output of the comparison circuit, the inverse output of the first trigger AND , to the second and third entrances of which are connected respectively pr -; my second trigger output and pulse generator output connected to 0 to the first input of the second element AND, 5 0 5 0 five the second and third inputs of which are connected to the direct outputs of the first and second triggers, respectively, the outputs of the first and second elements AND are connected to the counting inputs of the second counter with weights respectively 2 and 2, where L is the width of the argument, q is the number of bits from which sweep with an increased step, the output of the second counter is connected to the information input of the third register, the output of the second element AND is connected via the second delay element to the first input of the second element OR connected by the output to the synchronization input v the left register, the output of the first element I is connected via the third delay element to the synchronization input of the first register and the first input of the third element I, the second input of which is connected to the inverse output of the first trigger, the output of the third element H is connected to the second input of the second element OR, the output of the first element ki is connected to the installation input of the lower minor Aq bits of the second counter, the direct output of the first trigger is connected to the second input of the first NTK element, the output of which is connected to the counting input of the second trigger, about tl and - parts and so that, in order to expand the class of tasks to be solved by converting a given number of continuous monotonic functions, a third counter, a one-bit memory block, is entered into it , the decoder, the memory node block, the third switch, the Operty trigger, the fourth and fifth elements AND, the decoder input, the address input of the single-bit memory block and the control input of the third switch are connected to the input of the jj function of the converter, the output one bit bottom flash memory coupled to the control input of the second counter ratchet outputs cheny decoder connected to the enable input 20 sootvetst- vuyuschih node memory block address the inputs of which are connected to the output of the third counter, the outputs of the memory nodes of the block are connected to the corresponding information inputs of the third switch, the output of which is connected to the code input of the second adder, the output of which is connected to the information input of the second switch, the output of the first element I is connected to the counting input of the third trigger and to the first inputs of the fourth and fifth elements And, the second inputs of which are connected respectively to the direct and inverse outputs of the third trigger, the outputs of the fourth and fifth elements in AND connected respectively to the counting input of the third counter and the clock input of the second adder, the output of the second element OR is connected to the clock input, third register.