SU1631552A1 - Device for solution of integer problems of mathematical programming - Google Patents

Abstract

The invention relates to computing and can be used to solve integer math programming problems. The aim of the invention is to increase speed by eliminating

Description

consideration of obviously unsuitable combinations while maintaining the completeness of the search. The goal is achieved by the fact that the device for solving integer math programming problems, contains register 1, comparison circuit 2, summation node 3, element 4, groups of T registers 5 (where T is the dimension of the problem), T switches 6, T blocks analysis 7, T-1 flip-flops 8, T selectors 9, and T counters 10, introduced new links between the blocks. 4 il.

The invention relates to computing and can be used to solve integer math programming problems. The purpose of the invention is to increase speed by eliminating obviously unsuitable combinations from consideration while preserving the exhaustiveness of the search.

1 shows a block diagram of the device; figure 2 - structural diagram of the analysis block; FIG. 3 is a block diagram of the summation node; Fig. 4 shows the movement trajectory when solving a three-dimensional problem.

The device contains a register 1, a comparison circuit 2, a summation node 3, an AND 4 element, a group of registers 5f, switches 6, analysis blocks 7, triggers 8, selectors 9, counters 10, clock input 11, information outputs 12 and output 13 of the end problem solving.

Nodes 5-10 with their connections form blocks 14 and 15 of the formation of combinations. Analysis block 7 contains elements AND 16-18, trigger 19f elements OR 20 and 21, element 22 inequalities, information input 23, clock input 24, control inputs 25-27, and outputs 28 and 29.

The summation node 3 comprises a combinational adder 30, a register 31, an information input 32, an output 33 of the first sign bit, an output 34 of the high bit, an output of 35 lower bits, an output 36 of the second sign bit, and a control input 37.

The device is designed to solve problems whose mathematical formulation is as follows: find a | , i -1, ... ,, satisfying the condition:, oV,

V, v ;, a; i

- whole.

five

0

five

0

five

0

five

0

five

The device works as follows.

In the initial state, all the counters 10 are reset, the registers 5 record the values v ;, the registers 1 - D, the summing node 3 - V, the triggers 19 are in the zero state (there is no prohibition to change the contents of the counter 10), the triggers 8 - in the zero state (summation mode).

The device works in three stages. The first stage takes place on the leading edge of the clock pulse. Here, one of a is changed (by one) and the corresponding vj in the corresponding code is fed to the input of summing node 3. In the event of transfers, the operation modes of the blocks 15 (+ or -) change, i.e. the triggers 8 are flung. At the second stage, the next value of the o. On the combinational adder 30 is formed, and the necessary signs are fed to the inputs of the analysis units 7. At the third stage, on the trailing edge of the clock pulse, the new value about V is written to register 31 and the estimated value is obtained at nodes 2 and 4. In addition, the triggers 19 are set to the required state. They determine which of the auto changes in the next step.

Consider the operation of the device by the example of solving a three-dimensional problem () with the following initial conditions: V VЈ V -e 1, N {NЈ

 N3 4, V 4,5, D 0,25. This problem is degenerate and its solution does not exist. It is convenient to demonstrate all the main modes of the device.

At the initial moment a 0 the motion path is at the origin of the coordinates (Fig. 4). Trigger 19

the first analysis block 7 is reset, so the first clock pulse from the forward edge goes through the first switch 6 to the input of the first counter 10. At the summation node 3, a positive number V QV0 is written, at outputs 33 and 36, bit positions are zero. Therefore, the signal from the output 33 sets the summing mode of operation of the counter 10 and provides the transfer v | to the input of node 3, the summation in the reverse code. Thus, by 5P, the content of the first counter 10 is increased by one, the first selector 9 is connected to the input 32 of the summing node, and on the combinational adder 30 the formation of the value & Vf V - vj begins. The result is realized V - (point 4, figure 4). The next clock pulse, do not change

eleven

passes through the first switch 6. enters the second block 15 and, by $ n, performs the same actions, but with

in a values

and V

On

in the second counter (ag.)

the second stage is

unit.

in register 31 - (.

10a at the output of the Raman summata: Ј 0 (point 5 of Fig. 4).

ra 30 - ЈY

The latter leads to the fact that the output of the element And 18 of the first analysis block 7 is zero. Despite the fact that the sign of $ V has changed and the output of the element 22 of the unevenness of the first analysis unit 7 is one, but due to the lack of a clock signal at the input 27 of the first one, the transition to point 1 of figure 4 is done. Since 20 of the analysis block 7, at the output of AND 16, the change of the sign and V did not occur, then at the output of the element 22 inequalities in the first analysis block 7 - zero, is closed

element and 16

On the back front

25

that clock pulse t Cv j is written to register 31 and appears at outputs 33 - 35. If at some point it turned out that the value of & V (output 33 is zero), in the upper bits $ v - zeroes (at at 30 moves 34 are zeros), and the value recorded in the lower bits (output 35) is less than D, units will appear at the output of the comparison circuit 2 and element 4. The latter indicates that the solution was found - output 13. Since the conditions did not change after the first clock pulse, the second clock pulse performs the same actions with the only difference that in 40 the first counter 10 there are two, and in node 3 the summation - oVg value. V - Vj- v, (point 2, figure 4). A similar increase in a continues zero. As a result, Ј $ trigger 19 of the first analysis block is reset to the zero state, and oVj $ V v2 0 is written to register 31. The signal from output 33 sets the subtractive mode of the first counter 10 and the transfer mode through the first selector 9 in the forward code . The next clock pulse subtracts the unit from a and forms $ V V - v, 0 (point 6). The change of sign fV5 occurs at the output of the unequal element 22 of the first analysis block 7 is one, and since this change was associated with a, a clock signal is present at the input 27 of the first analysis block 7, AND 16 appears at the output of the element 16 which, having passed the element OR 20, by 23 sets the trigger 19 to the one state. On the next clock pulse, a changes and a transition to point 7, and so on. Finally, at the 12th step (Fig. 4), it turns out that aj Ne, a ,, 0, a. At the output of the elements And 16 and 17 of the first analysis block 7 there are units, therefore, the trigger 19 in Јe appears in a single state and does not change in the next clock cycle. In the second analysis block at the output of the element 1.8, there is one, since the operation mode of the second counter 10 is summing (the state of the first trigger 8), a. N2. Therefore, 3 flip-flop 19 is in a single state and ensures that the next clock is passed through until the next 1 / pv first counter 10 runs

a, NJ. In this case, since, at the output of the element 18 of the first analysis block 7, a unit appears, indicating that the first counter 10 cannot perform the operation of increasing its content. This signal, passed through the elements OR 21 and 20, is fed to the setup input of the trigger 19 of the first analysis block 7 and along the {} g, coming from the input 24, and sets the trigger 19 to the one state. At the same time, in node 3 the summation accumulates the value g V h

 V - (point 4, figure 4). The next clock pulse, do not change

eleven

passes through the first switch 6. enters the second block 15 and, by $ n, performs the same actions, but with

in a values

and V

On

in the second counter (ag.)

the second stage is

unit.

in register 31 - (.

and at the output of the combinational adder 30 - ЈU

: Ј 0 (point 5 figure 4).

The latter leads to the fact that the output of the element And 18 of the first analysis block 7 is zero. Despite the fact that the sign of $ V has changed and the output of the element 22 of the unevenness of the first analysis unit 7 is one, but due to the lack of a clock signal at the input 27 of the first 0 analysis unit 7, the output 16 And 5

0 5 0

five

0

five

sutstyuet zero. As a result, Ј $ trigger 19 of the first analysis block is reset to the zero state, and oVj $ V v2 0 is written to register 31. The signal from output 33 sets the subtractive mode of the first counter 10 and the transfer mode through the first selector 9 in the forward code . The next clock pulse subtracts the unit from a and forms $ V V - v, 0 (point 6). The change of sign fV5 occurs at the output of the unequal element 22 of the first analysis block 7 is one, and since this change was associated with a, a clock signal is present at the input 27 of the first analysis block 7, AND 16 appears at the output of the element 16 which, having passed the element OR 20, by 23 sets the trigger 19 to the one state. On the next clock pulse, a changes and a transition to point 7, and so on. Finally, at the 12th step (Fig. 4), it turns out that aj Ne, a ,, 0, a. At the output of the elements And 16 and 17 of the first analysis block 7 there are units, therefore, the trigger 19 in Јe appears in a single state and does not change in the next clock cycle. In the second analysis block at the output of the element 1.8, there is one, since the operation mode of the second counter 10 is summing (the state of the first trigger 8), a. N2. Therefore, 3 trigger 19 is in one state and ensures the passage of the next clock pulse to the next block 15 (a).

The thirteenth clock pulse, passing the first and second switches, yip the first trigger 8 and transfers block 15 to the subtractive mode of the counter 10 and to the forward code mode V through the second selector 9. On entering the second block 15, the clock pulse increases by one and forms the sum (figure 4). Since, a (0, then one from the output of the element And 17 sets the trigger 19 of the first analysis unit to one, prohibiting the change a- | at step 14. The subtracting mode of the first block 15 (trigger state 8) and the QV 0 drive t to the fact that the output of the element 22 inequality and the element AND 16, as well as the output of the element And 18 of the second analysis block 7 contains zeros, therefore the trigger 19 is in the zero state and the 14th step decreases hell (point 14) By this pulse, the change in a is resolved and a process similar to that described occurs.

Finally, the last version of the device operation mode occurs at the 29th step, at which a 0, 0 and a change of the V sign occurs. In this case, due to the unit at the output of the element And 18 of the first analysis unit 7, trigger 19 prohibits changing ac . The unit output 29 of the first analysis unit 7 is fed to the input 27 of the second analysis unit 7. The operation mode of the block 15 is summing (at the output of the trigger 8 is zero), and if about that, then at the output of the inequality element 22 and the AND 16 element of the second analysis block 7 there is a unit that

sets trigger 19 to zero and prohibits changing a. Thus, an increase in a to reach NЈ (which is not appropriate in this case) does not occur.

The rest of the solution search procedure is similar.

The indications of the device's end of operation are either the appearance of a sign of finding a solution from output 13, or the occurrence of transfer, from the senior unit 15, indicating, | no decision under given conditions.

d 0 5

0 5 0

five

0

Claims (1)

Invention Formula A device for solving integer math programming problems, containing a register, a comparison circuit, a summation node, an I element, a group of T registers (where T is the dimension of the problem), T switches, T analysis blocks, T-1 triggers, T selectors, and T counters, the counting input of the K-th (K 1, ..., T) counter is connected to the first input of the K-th switch, the information output of the K-th counter is connected to the information input of the K-th analysis unit and is the K-m information output of the device , the output of the K-th register of the group is connected to the information The input of the K-th selector, the output of which is connected to the information input of the summation node, the clock input of the first analysis block is connected to the control input of the summation node and is the clock input of the device, the low-order output of the summation node is connected to the first input of the comparison circuit, the control the input of the M-th (, ..., T) selector is connected to the output of the (M-1) th trigger, the output of the register is connected to the second input of the comparison circuit whose output is connected to the first input of the AND element, the output of the higher bits and the output of the first sign bit Yes, the summation node is connected respectively to the second and third inputs of the AND element, the output of which is the output of the device’s task completion, characterized in that, in order to improve performance by eliminating obviously unsuitable combinations from consideration while maintaining the exhaustive search, the output of the second sign bit the summation node is connected to the first control input of the K-th analysis unit, the first output of which is connected to the control input of the K-th switch, the first output of the K-th switch is connected to the input ohm connecting the K-th selector, the second output of the H-th (, ..., T-1) switch is connected to the information input of the (H + 1) -th switch and the clock input of the (H + 1) -th analysis block, the output of the first the sign bit of the summation node is connected to the control input of the first selector, the control input of the first counter and the second control input of the first the analysis unit, the third control VCHD of which is connected to the first output of the first switch, the information input of the first switch is connected to the clock input of the first analysis block, the second output of the N-th analysis block is connected to the third control; input (H + 1) -th. analysis unit, the second output of the M-th switch is connected to the counting input (M-1) -th | trigger, the output of which is connected to the control input of the M-th counter and the second control input of the M-th analysis block. & l .-ff   j