SU1756879A1 - Device for determination of linearity of boolean functions - Google Patents

Abstract

The invention relates to computing and 0 different technical data processing systems can be used as hardware support for computing. The purpose of the invention is the expansion of the class of solved problems due to the possibility of recognizing the belonging of a Boolean function to a class of linear arithmetic polynomial forms. The purpose of the invention is achieved by the fact that a Boolean differentiation unit 2, a comparison unit 5 and a reference values storage unit 4 are entered in the device comprising the synchronization unit 3 and the preliminary processing unit 1. 2 hp f-ly. 6 Il.

Description

The invention relates to the field of digital computing and can be used for hardware support of calculations in data compression systems, LSI topology synthesis, synthesis of discrete automata, image processing, decision making, control of robotic manipulators.

A device for calculating Boolean derivatives and containing a block generating unit, a group of inequalities, two multiplexers, OR elements and triggers is known.

However, the effectiveness of its use is low according to a number of criteria, which does not allow them to be used in practice. The reason is that the resultant vector obtained as a result of processing the vector of values of a Boolean function according to the mathematical model underlying this device has to be compared with p House of standards, the number of which is close to the number of Boolean functions belonging to the class of linear arithmetic polynomial forms .

The closest to the proposed one in terms of functions and technical essence is a device containing blocks for determining the non-conservation properties of the constant zero, unit, non-monotonicity, nonlinearity, and non-self-duality block (in the claimed object is a preprocessing block), the decoder of the completeness property sets, the set register completeness properties, basic group decoder, an assembly unit (in the claimed object — a synchronization unit) and corresponding links, the nonlinearity properties determining unit contains an adder group modulo two, the group of elements AND and the element OR, and the block for determining non-self-duals contains two modulo-two adders, the element OR and the element NOT.

This device allows you to determine the functional completeness of a system of Boolean functions. However, it is not suitable for the task for the following reasons.

The block for determining the nonlinearity property of a device allows recognition of functions belonging to a class of linear, but linear in the sense of representability by Zhegalkin linear polynomials, i.e. logical polynomials. The claimed object solves a different problem - it recognizes that it belongs to a class of linear arithmetic polynomials,

Partially it is possible to solve the problem with the help of the definition block

properties of non-dual property. But not all self-dual functions, but only a certain class of them, belong to linear arithmetic polynomials.

Thus, with the help of known technical devices, it is not possible to solve an important problem — to quickly determine the belonging of a given Boolean function to a class of linear arithmetic gender-nominal forms. This makes it difficult to solve the application-related problems of compressing logical data or binary images (as a system of Boolean functions), storing and processing topological images, processing logical data on structures that do not have logical operations, and so on.

The purpose of the invention is the expansion of the class of solved problems due to the possibility of recognizing the belonging of a Boolean function to a class of linear arithmetic polynomial forms.

The goal is achieved by the fact that in the device containing the synchronization unit and the preprocessing unit, the control input of the device connected to the trigger input of the synchronization unit, the information input of the device is connected to the input of the preliminary unit

0, the first output of the synchronization unit is connected to the output of the sign of the end of the device operation, a Boolean differentiation unit, a comparison unit and a reference value storage unit are entered,

5 whose output is connected to the second input of the comparator unit, the first input of which is connected to the output of the Boolean differentiation unit, whose information input is connected to the output of the block

0 preprocessing, and the control inputs from the first to the fourth boolean differentiation unit are connected respectively to the second to the fifth outputs of the synchronization unit, the second input of which is connected to the output of the comparator unit, in addition, the boolean differentiation unit contains a switch, modulo-two node and two registers, while the information input of the block is connected to

0 by the first, informational input of the switch, the second informational input of which is connected to the outputs of the unit and the modulo-adder node two, the first and second informational inputs of which are connected to the outputs of the first and second registers, respectively, the recording resolution inputs of which are connected to the first and second control inputs unit, respectively, the third control input of which is connected to the input of the shift control second

register, the information input of which is connected to the output of the first register, whose information input is connected to the output of the switch, the control input of which is connected to the fourth control input of the unit. The synchronization unit contains a pulse generator, three triggers, an n-bit counter, a multiplexer, three delay elements, three AND elements, an OR element, and an NOT element, whose input is connected to the installation input of the first trigger unit, the first input of the first element, and the output of the multiplexer, YHOHODY which is connected to the outputs of the n bits of the counter, the counting input of which is connected to the inputs of the first and second delay elements, the first input of the second element And the output of the pulse generator, the start input of which is connected to the start input unit whose stop sign input is connected to the first input of the third element AND, the second input of which is connected to the output of the OR element, the output of the third element AND is connected to the input of the second trigger, and the first input of the OR element, the second input of which is connected to the overflow output of the counter, the output of the second trigger is connected to the first output of the block, the output of the OR element is connected to the input of the stop of the pulse generator, the output of the first delay element is connected to the synchronization input of the first trigger, the output of which is connected to the second input ohm second element And the output of which is connected to the input of the third delay element and the second output of the block, the third output of which is connected to the input of the third trigger and the output of the third delay element, the output of the second delay element connected to the second input of the first element And whose output is connected to the fourth output block, the output of the third trigger is connected to the fifth output of the block.

The essence of the present invention is that the investigated Boolean function, given by a vector of its values on ordered sets of variables, is subjected to special processing, called parametric coordinate differentiation. As a result of this processing, if the function belongs to a class of linear arithmetic forms, a certain vector is obtained and to recognize the membership it is sufficient to compare it with the reference value.

The present invention is based on the following mathematical models of components and devices in general,

Any boolean function f (x) n of variables xi, x2хп can be represented in

the so-called arithmetic polynomial form, which has an analytical representation of the form

p (x) p (0) + p (1) xn + p (2) xn-i + p (3) xn-ixn +. .. +

, (2P About

4-рХ1 ... хп

2n-1

 2 p (DxV ...,

I 0

(one)

, 0)

where pv / b z, 2 is the set of integers such that p (x) with (0,1) on any set of variables and one can unambiguously get the vector x on the ordered sets of variables of the function f (x) (the column of values usually truth tables); lj-jth bit of the binary representation of parameter 1 (numbering with the highest ones);

XI1 XI, 1

x ,.

For example, the function is given in perfect disjunctive nominal form.

f (x) X1X2 V) 1X2,

has an arithmetic polynomial form

p (x) X1 + X2 - 2X1X2.

On any set of 00.01, 10, 11, the variables xi and X2, this expression has the value O or 1 and they are in ordered form nothing more than the vector of the value of the given function f (x).

Really

11: 0:

Thus, the arithmetic polynomial form differs from the well-known logical representations, for example the Zhegalkin polynomial, primarily by the presence of arithmetic operations. This form has a number of advantages. The most important for engineering practice is the possibility of a polynomial description of a system of functions and the solution of problems of minimizing (compressing) a system of Boolean functions based on this form. Therefore, it is necessary to quickly recognize a Boolean function that belongs to the class of linear arithmetic polynomial forms. The class of linear forms is determined by the ratio

RM

 + p, + ... + P (n) xi.

rule (2)

ten

Thus, the solution of the problem posed in principle comes down to constructing (calculating) for a given Boolean function of the polynomial (1) and testing its condition (2). However, such a path is not efficient in computational complexity. The basis of the approach implemented by the claimed device is a mathematical model based on the apparatus of logical differentiation.

In the matrix form, the parametric differentiation operator along the X coordinate of the vector of x values of the Boolean function f (x) has the form

fer L / f ST (mod 2), (3)

Lth)

where x (0 ... 0, 0 ... 01 1 ... 1) is the coordinate

differentiations with counts corresponding to ordered sets of variables xiх "; those. 2P, (p 0.0.1.2, ... n-1) differentiation parameter; M -, // - matrix of dimension 2 x 2P (n is the number of variables), formed by the recurrent rule

.Mji-- (d2),

I 1

m

ABOUT)

eleven

(four)

eleven

Let, for example, you want to find the derivative of the vector of values

- O 0 0 1 0 1 1 1,

where t is the symbol of transportation of a Boolean function of three variables with the parameter t

15

Perform the operation of differentiation according to the expression (3)

 at

.W35

It can be shown that the result can be obtained

... ir. € 2P, p 0,0,1 ... p-1,

This vector x belongs to the class of linear arithmetic polynomial forms.

Within this framework, we consider the organization of the computational process on a specific example.

Let a vector of values of a Boolean function of three variables be given

x 0 0 1 10 0 1 1 f.

The first computation step is to analyze the x ™ element of the xT vector. If it is zero (and in this case x 0 0), the next computation step is performed. Otherwise, i.e. if x 1, all elements of xT are inverted

In the second calculation step, the vector of values 3 is differentiated by the X coordinate with the parameter r -1 according to expression (3)

About 1 About 1 About

1 about 1

Since differentiation from r 1 did not lead to the desired result, and the number of steps was not exhausted (there are a total of 2 steps), and in this case p 3, the transition to the next step is performed.

In the third step, the operation of differentiation of the vector dx / dx obtained in the previous step of the calculations is implemented.

E / 9 m

a№gm

d

(one)

This calculation ends, since the initial vector of x values is reduced to 111111, which is a sign of its belonging to the class of linear arithmetic polynomial forms. This is easy to verify using the conversion engine.

The so-called Fourier transform in the conjunctive basis Cgp of the vector of values x allows to obtain the vector of coefficients p of the arithmetic polynomial form

10 L

which corresponds to a linear polynomial of the form P (X) X2.

Let us consider another example, which explains the essence of the mathematical model of a device, when the initial vector of x values does not belong to the class of linear arithmetic polynomial forms. Let it be defined as

 001 1.

Since x ™ 0, x is not inverted, and its first partial derivative with

Repeat this procedure for g 1 more

A W) - M U

j9 dx

(H

45

50

one

1 1 1 1 1 1 1 1 1 1 1 1 1

55

If the value of m 2 we get

L / e / am / el

(a7 /; (V

(L (

0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 1 About

one

This calculation ends, since the number of operations in p 3. The result is not equal to 1 ..., therefore, the initial vector does not belong to the class of linear arithmetic polynomial forms. This is easily verified by performing the Fourier transform on the conjunctive basis ten over it (n 3)

P K2ZH:

00000 00000 00000

10,000 01,000

0-1,100

0-1010

1 1-1-1 1

about 1 about

-one

one

-one

-one

0

those. p (x) xs - x2xs + xi - x1xs - xiX2 is not a linear arithmetic polynomial.

FIG. 1 shows a block diagram of the device; in fig. 1 preprocessing unit; in fig. 3 —boole differentiation unit; in fig. 4 is a block diagram of the synchronization unit; in fig. 5 is a timing diagram of the operation of the synchronization unit; in fig. 6 - device operation.

The device (Fig. 1) contains a preprocessing unit 1, a boolean differentiation unit 2, a synchronization unit 3, a reference value storage unit A and a comparison unit 5, the output of which is connected to the second input of the synchronization unit 3, the start input of which is connected to the control the input of the device, and the first output of the synchronization unit 3 is the output of the indication of the end of operation of the device, and from the second to the fifth outputs of the synchronization unit 3 are connected respectively from the first to the fourth control inputs of the unit 2 boolean differential ation whose output is connected to a first input of the comparator 3, a second input coupled to an output of the unit and the storage of reference values, and a fifth (data) input of the block 2 boolean differentiating connected to the output pre-processing unit whose input is the data input

devices.

The preprocessing unit 1 ensures the transfer of the vector of values ZG x ... from the input to the output without changes in case the element O,

or in inverted form, if x 1.

The Boolean differentiation unit 2 provides a logical processing of the vector H or x, arriving at its fifth (informational) input in accordance with

mathematical model.

The synchronization unit 3 is designed to generate signals controlling the operation of the device.

Unit 4 storage reference values

it is intended for storing a 2P code of type 1 .... The design is made in the form of a rigid connection of discharge buses of a block with a second to 2 nd bus with a high logic voltage level bus

(logical unit).

Comparison unit 5 is designed to analyze the coincidence of the codes arriving at its first and second inputs. When the codes at its output coincide, a signal of a logical unit is formed.

The preprocessing unit 1, the boolean differentiation unit 2 and the synchronization unit 3 have features of circuit design and operation.

Block 1 preprocessing (Fig. 2) contains 2P adders 11 (I 1,2) modulo two, the second inputs of which are interconnected and connected to the first input of the first adder 1i modulo two; The first input of the first modulo-2 adder is the first input of the preprocessing unit 1.

Block 1 preprocessing works as follows. When mm arrives at its input, the elements of the vector of values Γ Do ° V1 ... x (2n Y of the Boolean function of n variables, the values of the first element are analyzed.

5 two cases.

In the first case, when x 0, modulo two with zero zero is performed on modulators two from 1 to 12P with values of 3 V vector elements

As a result, all the elements of the vector x are transmitted to the output of the preprocessing unit 1 unchanged.

In the second case, when x ™ 1, modulo two moduli of two logical units with values of vector elements are performed on modulators two from 1j to 12P. As a result, inverse values of elements of vector 4x are transmitted to the output of preprocessing block 1 (0) D..x 2p-15 t.

Thus, the preprocessing unit 1 transmits the vector x from the input to the output in a forward or inverse code, depending on which the zero or one value, respectively, has the first element of the vector x. The Boolean differentiation unit 2 (Fig. 3) contains the switch 6, the node 7 modulators two, the first 8 and second 9 registers, while the fifth (informational) input of the block is connected to the first information input of switch B, the second information input of which is connected to the outputs of the block and node 7 of the adders modulo d a, the first and second information inputs of which are connected to the outputs of the first 8 and second 9 registers, respectively, the second inputs (write enable inputs) of which are connected to the first and second control inputs of the block, respectively, the third control input of which is connected to the third input (control input shift) the second register, the first (informational) input of which is connected to the output of the first register 8, the first (informational) input of which is connected to the output of the switch b, the third (control) input of which is connected to the fourth rtym control input unit.

Switch 6 is designed to transfer information from the first or second information inputs to the output, respectively, at a low or high Logic level at its third control input.

The modulo-two adder unit 7 provides bit-wise modulo addition of two codes to its first and second inputs.

The first register 8 is intended for receiving and short-term storage of the code x coming from the first (informational) input by a signal at the second input (recording permission input).

The second register 9 is intended for receiving, short-term storage and conversion (shift) of the code arriving at the first (informational) input on a signal at the second input (input of recording resolution). Shifting the content towards the lower bits is performed on a signal at the third input (the input of the shift control). 5Block 2 differentiation

works as follows. Previously, all zeros of the first 8 and second 9 registers are written in zeros. From the fourth information input of the block via path 10, the first input — the output of switch 6 (on the third — the control — input of switch 6 — a low logical signal level), the first register 8 records the code of the analyzed vector, or 15, time ti (Fig. 5). ).

At time ti Ata, the signal at the second control input of the 2 Boolean differentiation unit overwrites the code of the Guise vector of the first register 8 into the second register 9. At time ti + At2, the signal at the third control input of the block 2 is executed a shift by one bit in the direction of the lower contents of the second register 9. At the output 5 of the node 7 modulo-two adders, the result is e) 7 dx.

Next, the operation of the 2 unit of differentiation consists in writing the result to the first 0 register 8 (time point ta), rewriting it from the first register 8 (ta + Ata) to the second register 9, shifting by one bit towards the lower contents of the second register 9 (moment of time ta + Ata) and in bitwise order 5 modulo summation two contents of the first 8 and second 9 registers and node 7 modulo adders two. Thus, the result of the form d (Eh / yx) / Eh is formed. The control signals for writing to the first 0 register 8, writing to the second register 9, shifting the contents of the second register 9 by one or several bits, respectively, on the first, second, and third inputs of the Boolean differentiation unit 2 are repeated 5 cycles.

The synchronization unit 3 (FIG. 5) contains a pulse generator 10, the first 11, the second 12 and the third 13 triggers, the counter 14, the multiplexer 15, the first 16, the second 17, the third 18 0 delay elements, the first 19, the second 20 and the third 21 elements And, the element OR 22 and the element NOT 23, the input of which is connected to the installation input to the unit of the first trigger 11, the first input of the first element AND 5 19 and the output of the multiplexer 15, the inputs of which are connected to the outputs of the bits of the counter 14, the counting input of which is connected to the inputs of the first 16 and second 17 delay elements, the first input of the second

20 of the And element and the output of the pulse generator 10, the start input of which is connected to the block start input, the stop sign input of which is connected to the first input of the third And element 21, the second input of which is connected to the output of the HE element 23, the output of the third element And 21 is connected to the input of the second trigger 12 and with the first input of the element OR 22, the second input of which is connected to the overflow output of the counter 14, the output of the second trigger 12 is connected to the first output of the block, the output of the element OR 22 is connected to the input of the stop of the pulse generator, the output of the first ele The delay element 16 is connected to the synchronization input of the first trigger 11, the output of which is connected to the second input of the second element AND 20, the output of which is connected to the input of the third delay element 18 and the second output of the block, the third output of which is connected to the input of the third trigger 13 and the output of the third element 18 delay, the output of the second delay element 17 is connected to the second input of the first element And 19, the output of which is connected to the fourth output of the block, the output of the third flip-flop 13 is connected to the fifth output of the block.

The pulse generator 10 is designed to form a regular pulse train and has a first start input and a second stop input.

The first trigger 11 is designed to control the operation of the second element AND 20 in order to generate pulses on the first and second outputs of the synchronization unit 5. In the zero state, trigger 11 blocks the formation of pulses on the first and second outputs of synchronization unit 5 (Fig. 5). Structurally, this is a synchronous D-flip-flop With installation and reset (measures, K155TM2), with the levels of logical zero and one being continuously supplied to inputs D and R, respectively. The first input (the installation input to the unit) of the first trigger 11 is the installation input S, and the second input is the synchronization input C. The initial state of the first trigger 11 is a unit. The second 12 and third 13 flip-flops are designed to generate signals at the fourth and fifth outputs of the synchronization unit 3, respectively. Structurally, these are D-flip-flops, which are set to one at the front at their input. Their initial state is zero,

The counter 14 is designed to regulate the operation of the device. Structurally, it is a p-bit counter of the summing type with a counting input, (n + 1) -th output of the counter 14 is the overflow output. Its initial state is zero.

The multiplexer 15 is designed to form at its output a signal controlling the operation of the first trigger 11, the third element 21 and the element NOT 23. The multiplexer 15 forms a logical zero signal at its output for the following values at its address inputs:

0n-1

2, 44 + 2, (2P + 1). In all the others

p 1

cases at the output of the multiplexer 15 is a logical unit signal (table).

5 The operation mode of the multiplexer 15, which has n address and 2P information inputs, is ensured by the fact that the address inputs from the first to the nth are connected to the corresponding outputs (from the first to the nth)

0 counter 14. The information inputs of the multiplexer 15 are connected to the potentials of logic levels in accordance with the table.

Structurally, the multi-plexer 15 (2П - 1) resolution can be achieved using a cascade connection of multiplexers.

The first 16, second 17 and third 18 delay elements provide a delay.

o input signal at time Ati, At2nAts respectively.

The first 19, the second 20 and the third 21 elements And are designed for a logical analysis of the incoming signals at the inputs

5 by performing a conjunction operation.

The element OR 22 is intended for the logical analysis of input signals by performing a disjunction operation on them.

0 The functions of the synchronization unit 3 are to form the control signals for the operation of the Boolean differentiation unit 2. The pre-trigger 11 is set to the state of a logical unit, the second 12 and the third 13 triggers are set to the logical zero state, and the counter 14 is set to the zero state. Synchronization unit 3 is triggered by a signal at the start input of the generator 10 and 0 pulses. At the first output of the synchronization block 2, a sign of the recognition result is formed, at the second and third outputs, respectively, the write signals to the first 8 and second 9 registers of the block

5 2 Boolean differentiation; a shift signal in the second register 9 is formed at the fourth synchronization output 3; a signal regulating the operation of the switch 6 is formed at the fifth output. The number of shift signals m generated at the fourth output of the synchronization unit 3 is determined by the code value at the outputs counter 14. Thus, the write and shift signals generated on the second, third and fourth outputs of the synchronization unit 3 form a group of control signals governing the operation of the unit 2 about differentiation during the execution of the operation of Boolean differentiation with the parameter r.

Consider the formation of the first group of control signals at the outputs of the synchronization unit 3. These signals provide control over the operation of the Boolean differentiation unit 2 during the execution of the boolean differentiation operation with the parameter r 1. This is due to the following operation of the elements of the synchronization unit 3.

At time point to (Fig. 5), the device starts up. As a result, the pulse signal generated at the output of the generator 10 is fed to the inputs of the counter 14, the first 16. the second 17 delay elements and the second element 20, from the output of which the pulse signal is transmitted to the second output of the synchronization unit 3 (at the second input of the second element 20 - high logical level of the signal coming from the output of the first trigger 11 (from being in the state of the logical unit). In addition, the pulse signal from the output of the second element I 20 enters the input of the third delay element 18. At the time Ati + Ata (A t , - the delay time on the third delay element 18) the pulse signal from the output of the third delay element 18 is transmitted to the third output of synchronization unit 3, as well as to the input of the third trigger 13. which is set to the state of logical one, and to the fifth output of synchronization unit 3 a high logical level of the signal (it is maintained at the fifth output of the synchronization unit 5 until the completion of the Boolean differentiation). At the first output of the synchronization unit 3, the logic level of the signal is kept low. Consider the formation of a signal at the fourth output of block 3 synchronization. According to the pulse signal generated at the output of the pulse generator 10 at the time ti (Fig. 5), the counter 14 changes from the state 0 ... 0 to the state 0 ... 01, the Code 0 ... 01 from the output of the counter 14 It is transmitted to the inputs from the first to the nth multiplexer 15, at the output of which a high logical level of the signal is formed (table), which is transmitted to the first input of the first element And 19, To the second input of the first element And 19 at time ti + A t2 from the output The second delay element 17 (Fig. 5) receives a pulse signal, which is transmitted 5 from the output of the first element 19 on the fourth output synchronization unit 3.

In addition, a high logic level from the output of multiplexer 15 is transmitted to the installation input to unit 10 of the first trigger 11, and the signal at the output of the first trigger 11 does not change. At the time ti + Ati, the synchronization input of the first trigger 11 receives a pulse signal from the output of the first element

15 16 delays, and the trigger 11 switches to a logical zero state. As a result, at time t2, a pulse signal is not received at the second output of the synchronization unit 3.

0 Thus, at times ti - t2, the first group of control signals is formed at the outputs of the synchronization unit: at time ti - at the second output; ti + At3 - at the third exit, in

At 5 ti + A t3, the shift signal at the fourth output (pulse signals) and at the fifth output forms a high logic potential level.

At time t2, the counter 14 switches from the state 0 ... 01 to the state 0, .. 010, and at the output of the multiplexer 15 a low logic level is generated, which causes the following changes in the circuit: the first trigger 11 is set to

5 state of the logical unit; at the output of the first element And 19 a low

- the logical level of the signal that blocks the formation of pulses at the fourth output of the synchronization unit 3 (Fig. 5). On

0, the output of the element NOT 23 generates a high logical level of the signal, which is transmitted to the second input of the third element AND 21. As a result, a signal arriving at the first input of the third element And 21 from the input of the stop sign of the synchronization unit 3 (the the signal is a sign of the result of recognition from the output of the unit 5 of the comparison). In this case, two cases are possible when at 0 the comparison sign is zero, and when the comparison sign is equal to one. Consider the first case, i.e. the case when the first input of the third element And 21 receives a low logical level signal. Then, at the output of the third element And 21, the logic level of the signal is low. As a result, the synchronization unit 3 is prepared for the formation of the next first group of control signals.

At times ta, t3 + At3, t3 + At, the outputs of synchronization unit 3, the second, third and fourth outputs, respectively, form signals from the second group of control signals (this group of signals provides control over the operation of unit 2 of differentiation with differentiation with parameter g 1). The formation of the second group of control signals is similar to the formation of the first group of control signals, however, the third trigger 13 in this case does not change its state (the state of the logical unit).

Consider the second case, when the first input of the third element And 21 receives a high logical signal level (recognition sign (time instant AND Fig. 5). This signal comes from the first input to the output of the third element And 21 (the second input of the And 21 element is high the logical level of the signal that comes from the output of the element NOT 23, the input of which is a low logical level of the signal from the output of the multiplexer 15.) From the output of the third element 21, the high logical level of the signal is transmitted to the first input of the element OR 22 and further to the input For stopping the pulse generator 10. Thus, the operation of the synchronization unit 3 is completed.

Consider also the case when the first input of the third element And 21 all the time remains a low signal level, i.e. The sign of the recognition result for 2H clock cycles is not formed (the function is not linear). In this case, at the instant of time t.b, the counter 14 goes to the state 1 ... 1 (211 -1). At the moment of time, those at the (n + 1) -th output of counter 14 generate an overflow signal (high logic level of voltage). This signal is fed to the second input of the element OR 22 and then from its output to the input of the stop of the generator 10 pulses. In this case, a low logic level of the signal is formed at the first output of the synchronization unit (a sign of a negative recognition result).

Consider the operation of the device in the aggregate of its components, highlighting in its operation a number of stages.

At the first stage of operation, the preliminary processing unit 1 analyzes the element x (0} of the vector - x {0) x (1).,. X (2n 1) t. In her tone, the output of the preprocessing unit 1 is transmitted by the vector x without changes. Otherwise (x 1) on

its output is transmitted by the inverse of the vector, i.e. x "..

The second stage is performed once. Differentiation of the vector x or x by differentiation unit 2 in accordance with the mathematical model (3) with r 1. This is provided by a group of control signals generated by synchronization unit 3, the result is transmitted as a vector x x dx to the first input of comparator unit 5.

At the third stage of the calculation, the comparison unit 5 performs an analysis for the coincidence of the vector dlt / dx at the first input with the reference vector he 1 ... transmitted to the second input from the output of the unit 4 of the storage of reference values. In case of mismatch of the vectors dx / dx, the output of the comparison unit 5 maintains a low logical level of the signal (a sign of continuing logic processing). If the vectors dx / dx and & at the output of the comparison unit 5, a logical unit signal is generated - a sign that the recognizable vector 5t belongs to the class of linear arithmetic forms.

The number of stages of operation of the device is determined by the structure of the vector x being analyzed.

FIG. 6 shows the computational process of recognizing the linearity of the vector x 00001111 t and shows the change at each step of calculating the contents of the first in and second 9 registers of Boolean differentiation unit 2. 2. The result of modulo adding two contents of the first 8 and second 9 registers at each step goes to the first the input of the comparison unit 5 and the second input of the first register 8, then the contents of the first register 8 is rewritten into the second register 9. The content of the last one is shifted by r bits, namely 1, 1 and 2 bits according to the mathematical model (3). The calculation process ends at a trailing step when the result of the form d (d (dx / dx) / Eh) / d (2 x) is equal to the reference vector & 11111111 t.

Thus, the present invention is characterized by the expansion of the class of tasks to be solved in comparison with analogues and the prototype, which provides an operational analysis of the belonging of a given Boolean function to a class of linear arithmetic polynomial forms; simplicity of technical solutions and manufacturability; increase the speed of analysis.

Invention Formula

1. A device for recognizing linearity of Boolean functions, containing a synchronization unit and a preprocessing unit, the control input of the device connected to the start input of the synchronization unit, the information input of the device connected to the input of the preprocessing unit, the first output of the synchronization unit connected to the output of the sign termination of the operation of the device, characterized in that. in order to expand the class of solved tasks due to the possibility of recognizing the belonging of a Boolean function to a class of linear arithmetic polynomial forms, the device contains a boolean differentiation unit, a reference value storage unit and a comparison unit, while the output of the preprocessing unit is connected to the information input of a boolean differentiation unit whose output is connected to the first input of the comparison unit, the second input of which is connected

with the output of the storage unit of reference values, the output of the comparator unit is connected to the input of the stop indication of the synchronization unit, the second to the fifth outputs of which are connected to the first to fourth control inputs of the corresponding Boolean differentiation unit.

2. Device pop. 1, characterized in that the Boolean differentiation unit contains a switch, a modulo-summing node two and two registers, wherein the information input of the block is connected to the first information input of the switch, the second information input of which is connected to the outputs of the block and modulo-adder node two, the first and second informational inputs of which are connected to the outputs of the first and second registers, respectively, the recording resolution inputs of which are connected to the first and second control inputs of the block, respectively, the third control which input SOR is dinine with the shift control input of the second register, the information input of which is connected to the output of the first register, whose information input is connected to the output of the switch, the control input of which is connected to the fourth control input of the unit.

3. The device according to claim 1, characterized in that the synchronization unit includes a pulse generator, three flip-flops, an r-bit counter, a multiplexer, three delay elements, three AND elements, an OR element and an NOT element, whose input connected to the input set1 in 1 of the first trigger, the first input of the first element And the output of the multiplexer, the inputs of which are connected to the outputs of the n bits of the counter, the counting input of which is connected to the inputs of the first and second delay elements, the first input of the second element And and the output of the pulse generator, start input which is connected to the start-up input of the block, the input of the stop sign of which is connected to the first input of the third element AND, the second input of which is connected to the output of the element NOT, the output of the third element AND is connected to the input of the second trigger and the first input of the OR element, the second input is connected to the overflow output the counter, the output of the second trigger is connected to the first output of the block, the output of the OR element is connected to the stop input of the pulse generator, the output of the first delay element is connected to the synchronization input of the first trigger, the output which is connected to the second input of the second element And, the output of which is connected to the input of the third delay element and the second output of the block, the third output of which is connected to the input of the third trigger and the output of the third delay element, the output of the second delay element connected to the second input of the first element And whose output connected to the four-output block, the output of the third trigger is connected to the fifth output of the block.

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Claims (4)

Claim 1. A device for recognizing linearity of Boolean functions, comprising a synchronization unit and a pre-processing unit, wherein the control input of the device is connected to the start input of the synchronization unit, the information input of the device is connected to the input of the unit. Pre-processing, the first output of the synchronization unit is connected to the output of the sign of the end of work devices, characterized in that, in order to expand the class of problems being solved due to the possibility of recognizing the membership of a Boolean function to a class of linear * arithmetic polynomial forms, device. contains a Boolean differentiation unit, a storage unit for reference values and a comparison unit, wherein the output of the pre-processing unit is connected to the information input of the Boolean differentiation unit, the output of which is connected to the first input of the comparison unit, the second input of which is connected to the output of the reference unit . ny, the output of the comparison unit is connected to the input of the stop sign of the synchronization unit, the second to fifth outputs of which are connected from the first to fourth control inputs of the block, Boolean differentiation, respectively. 2. The device according to claim 1, wherein the Boolean differentiation unit comprises a switch, a summing unit modulo two and two registers, while the information input of the block is connected to the first information input comm; tator, the second information input of which is connected to the input of the third trigger and the horn is connected to the outputs of the unit and node 25 which is connected to the output of the element NOT, the output of the third element AND is connected to the input of the second trigger and the first input of the OR element, the second input of which is connected to the output of the counter overflow, the output of the second trigger is connected to the first output of the block, the output of the OR element is connected to the stop input of the pulse generator , the output of the first delay element is connected to the synchronization input of the first trigger, the output of which is connected to the second input of the second element And, the output of which is connected to the input of the third delay element and the second output eye, third exit kotovyhodom third delay element v'ysummatorov modulo two, first and second course vtorogo'elementa delay coupled to a second input of the first element and the: output -which s0eDyn y'S ^ ^"h! With the fourth output, the information inputs of which are connected to the outputs of the first and second registers respectively, the recording permission inputs are 45 blocks, the output of the third trigger is connected to which are connected to the first and second control inputs of the block, respectively, the fifth output of the block. Measure number . ; Multiplexer 15 Address Entries! counter outputs Ϊ4) Exit 1  2 ... n ’1 η 0 0 0 · · · 0 0 0 1 0 0 · · ♦ 0 1 • 1 2 0 0 · · · 1 . 0 0 • 3 0 0 "· ♦ 1 1  1 4 0 0 · 1 about 0 0  ♦ • <· • • • η - 1 - * "W * - _ _ about 4 + Σ (2 ^P +1) .......... P = ’. Table continuation Z Zfer / w ^ W ///// a7 £ -йМ8№№? // 4 ? ! 3 8ifXoJ / I 8z / n72 i ip: 1-u me U 4Fig; 4 ' 8wi? sv / umg 8 * 01? 0pl / 3mtm fumv / t SbjXU ^ / _t (trigger //} Gmerapur., Ishrish. Counters tywrtwx · op / 5 / th · ЗМРрЖШ / 6 Trigger // To— Z1 8b / hv32 2 · ΰ тя тя и м р & & &> 24. -ί prnuwf „__— J_Z_ OIZH 0UPfi2u £? No. 7U I -—— 7 η _1 ..... 1—1 — l_J_J_q_V 8 / W // / 2/3 ^ 2- / ~ Ep00U7 / 7 ^ p ~ 3j ^; zrz ~ Hk_nr. JL_J, „J ...... 1-1 f pmawpifiu? , __ J._. I. Jnuurt / regmtrg / Jtffufi 8 reg7i? Pp J. L I. J-li-J— Щ 1-LL1 -.— Г .. L1 ..... L rtfae / rmmrer 4 i ύ i i - - “game 5 ί + 6 ' Compiled by D. Kuzmitsky Editor L. Gratillo Tehred M. Morgenthal Corrector E. Papp Order 3088 Circulation Subscription VNIIIPI of the State Committee for Inventions and Discoveries at the State Committee for Science and Technology 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and Publishing Combine Patent, Uzhgorod, 101 Gagarin St.