SU1059580A1 - Probabilistic device for simulating complex stochastic systems - Google Patents

Abstract

1. A PROBABLE DEVICE FOR MODELING COMPLEX STOCHASTIC SYSTEMS containing a sensor of uniformly distributed random numbers, a comparison unit, the first input of which is connected to the sensor output of uniformly distributed random numbers, a memory block, the first number register, the input of which is connected to the output of the memory unit characterized by the fact that, in order to improve the speed, it is in addition. It contains the second number register, the first and second address generation units, the number switch, the address switch, the synchronization unit, the first output of which is connected to the sensor input of uniformly distributed random numbers and the first inputs of the first and second generation units, the second output is connected to the control- the inputs of the first number register, the address switch and the second address generation unit, and the third output - with the control inputs of the number switch, the second number register and the first generation unit address the second input of the comparison unit is connected to the switch output of the number, and the output is connected to the second inputs of the first and second address generation units, the outputs of which are connected respectively to the first and second inputs of the address switch, the output of the address switch is connected to the input of the memory block to the output of which the input of the second register of the number, the outputs of the first and second registers: the numbers are connected respectively to the first and second inputs of the comm switch of the number. 2i The device according to claim 1, characterized in that, the block of the odds (the address of the address contains the first and second registers, the first and second And elements and the delay element whose input is connected to the first input of the first register and is the first input of the block, and the output is connected to the first inputs of the first and second elements And, the second inputs of the first and second elements And are connected respectively to the second and third inputs of the first register, and the outputs are connected respectively to the first and second inputs of the second register, the group of outputs of which is with the output 00 of the block, the group of inputs of the first register is the second input of the block, and the group of outputs is connected with the group of inputs of the second register, the control inputs of the first and second registers are connected to the control input of the block.

Description

The invention relates to computing and can be used in the construction of stochastic computers, probabilistic models of complex systems, and also as a specialized unit connected to a computer.

A device is known that allows generating random numbers with arbitrary required distribution laws, comprising a multichannel generator of random impulse streams, AND elements, OR element, probabilistic gate, random number generation register, AND register scheme, memory address forming device, and clock pulse generator Cl.

The disadvantage of this device is the low speed due to the sequential procedure of forming a random number.

The closest to the present invention is a device for probabilistic modeling, comprising a device (block / control, sensor (generator) of uniformly distributed random numbers, a comparison, a mask register, a number register, a memory device (memory block J and address block (address register) , divided into two parts - the older and younger.

The device allows generating random number sequences with the required distribution laws, as well as Markov processes. In this case, an inverse function method is implemented, based on a comparison of uniformly distributed random numbers with the values of the reproduced distribution function F (x), finding the interval for which F (x.) F F (X | and issuing the values corresponding to this interval). .. The device also allows you to simulate 2 different laws of distribution, where K is the size of the older part of the register. The required law is selected by writing the number of the required law to the older part of the address register. Two bits of the random number C2 are simultaneously rotated.

A disadvantage of the known device is that inside the device nodes — a memory device, a number register, a comparison unit, an address unit — operate strictly sequentially, which reduces speed.

The purpose of the invention is to increase speed.

The goal is achieved by the fact that the probabilistic device

for simulating complex stochastic systems, containing a sensor of uniformly distributed random numbers, a comparison unit, the first input of which is connected to the sensor output of uniformly distributed random numbers, a memory unit, the first register of the number whose input is connected to the output of the memory unit, further comprises a second register numbers, first and second address generation units, number switch, address switch, synchronization unit, the first output of which is connected to the sensor input of uniformly distributed single numbers l and the first inputs of the first and second address generation units, the second output is connected to the control inputs of the first number register, switch c1.dres and the second address generation unit, and the third output with the controllers Bhod and number switch, second number register and the first forming unit address, the second input of the comparison unit is connected to the switch output of the number, and the output is connected to the input inputs of the first and second address generation blocks, the outputs of which are connected respectively to the first and second inputs of the address torus; The commutator of the switch is connected to the input of the memory unit, the output of which is connected to the input of the second number register, the outputs of the first and second number registers are connected to the first and second input AND of the number switch, respectively.

The address generation unit contains the first and second registers, the first and second And elements and the delay element, whose input is connected to the first input of the first register and is the first input of the block, and the output is connected to the first inputs of the first and second And elements, the second inputs of the first and second The second elements And are connected respectively to the second and third inputs of the first register, and the outputs are connected respectively to the first and second inputs of the second register, the output group of which is the output of the block, the input group of the first register is in orym input unit, and a group of outputs coupled to inputs of the second register grpoy, control inputs peryogo and second registers are connected to the control input. block.

FIG. 1 is a block diagram 60 of the device} in FIG. 2 is a functional diagram of an address generation unit / in FIG. 3 - functional block diagram K: j synchronization; in fig. 4 shows the time diagrams of signal controllers of the OS. The device (Fig. 1) contains a sensor 1 of uniformly distributed random numbers, a comparison block 2, a switch 3 numbers, the first 4 and second 5 number registers, a memory block 6, an address co 7, the first 8 and the second 9 forming blocks addresses and block 10 synchronization. Each block of the formation of the address (Fig. 2) contains the first 11 and second 12 registers, the delay element 13 and the first 14 and second 15 elements I. Each of the registers of the address formation block consists of groups of 16 triggers. The synchronization unit of FIG. 3 contains a pulse generator 17, a trigger 18 and a delay element 19. The output of sensor 1 of uniformly distributed random numbers is connected to the first input of comparator 2, the second input of which is connected to the output of switch 3 and the output to the second inputs of the first 8 and second 9 blocks of address formation. The first output of the synchronization unit 10 is connected to the input of the sensor 1 of uniformly distributed random numbers and the first inputs of the first 8 and second 9 address formation units, the outputs of which are connected respectively to the first and second inputs of the address switch 7. The output of the address switch 7 is connected to the memory block input, the output of which is connected to the information inputs of the first 4 and second 5 number registers. The outputs of the first 4 and second number registers are connected respectively with the first and second inputs of the switch-3 numbers. The second output of the synchronization unit 10 is connected to the control inputs of the first register 4 numbers, the switch 7 addresses and the second block 9 form the address and the third output is connected to the control inputs of the switch 3 numbers, the second register 5 numbers and the first block 8 form the address. The input of the delay element 13 to the address generation unit is connected to the first input of the first register 11 and is the first input of the first register 11 and is the first input of the block, and the output is connected to the first inputs of the first 14 and second 15 elements And the second inputs of the first 14 and second The 15 And elements are connected respectively to the second and third inputs of the first register 11, and the outputs respectively to the first and second inputs of the second register 12, the group of outputs of which is the output of the block. The group of inputs of the first register 11 is the second input of the block, and the group of outputs is connected to the group of inputs of the second register 12. The control inputs of the first 11 and second 12 registers are connected to the control input of the block. The synchronization unit 10 may be made of a wide range of known homonymous blocks. An example implementation of a synchronization unit 10 satisfying the requirements of the proposed device is shown in Fig. 3. The device operates as follows. Sensor 1 of uniformly distributed random numbers forms indepen dently uniformly distributed random numbers on IntepJaE 0-1. When the device is turned on, the output of the sensor 1 produces the first random number. Further synchronization of its operation is performed by pulses C, coming from the first output of the synchronization unit 10. The next number is generated by sensor 1 at the end of signal C. Switch 3 connects the output of register 2 to register input 4 or register 5 output. Address switch 7 connects the output of block 8 or block 9 of address formation to the address input of memory block b. When f receives a single signal at the control input of any of the switches, the first input of the switch is connected to its output; when the control input is zero, the second input of the switch is connected. The code words that configure the device to form random numbers with the required distribution function are recorded in a memory block. In one cell is written In 1 code words. Registers 4 and 5 of the number serve to store code words read from the memory block. At the resolving single signal at the second output of the control unit 10) the recording of code words from the output of the memory block b is performed in register 4, with the resolving single signal at the third output of the block 10 (.1 the recording of code words is performed at the register 5. Block 2 compares E 2-1 values; a, A, ..., Ag with a uniformly distributed number S, R as a result of comparison, at the output of block 2, a t-bit word q is formed according to gfilo O, with O S: l. 1, with e -1, with A Ag, 2, with A g 1.

The address generation blocks 8 and 9 serve to generate a random number and in turn are the address registers of the memory block 6. At each operation cycle of the device, m bits of a random number are formed in one of the address formation blocks, the other is the address register of memory block 6, which is provided by connecting the outputs of the corresponding address block by switch 7 to the input of memory block b. Registers 11 and 12 of blocks 8 and 9 are made on single-ended synchronized 1) -triggers of group 16 with synchronous installation inputs. Information recording into the trigger of group 16 can be carried out both on the setup R- and 5-inputs, and on the-input on the sync pulse at the C-input with the enable signal on the V-input of the trigger.

A random n-bit number is formed in K steps, n with m. The algorithm of formation is based on the combination of the methods of conditional probabilities and inverse functions. The simulation of m bits inside the step is performed by the inverse function method by comparing a uniformly distributed number I with the values of the conditional distribution function F (xgde 5 is a random number generated in the previous steps. Calculation of conditional distribution functions

The p5 (x |) is performed according to the conditional probabilities method.

The proposed device at the expense of combining the time of the read operation from the memory block with the procedures of comparing the codes and forming the bits of the random number has a greater speed than the known ones. So, in the continuous generation mode, if T is the time

0 read codes on the memory block

It is the number of accesses to the memory block when forming one random number, C2 is the time of comparing codes and forming m bits of a random number, then, neglecting the switching time of the switches, the average time of forming the number in the proposed device is calculated by the formula

T 4

1 7 / g; 2;

at

at t- ;, c.

The average time of formation of a random number in a device without combining Tg-k (.f) therefore, „„ „.. ..„ „„ for performance

dt

boost

2U The proposed device is expediently used in all cases when it is necessary to form at high speed sequences of random numbers with an arbitrary desired distribution function.

Rig. 2

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Claims (2)

1. A PROBABILITY DEVICE FOR MODELING COMPLEX STOCHASTIC SYSTEMS, comprising a sensor of uniformly distributed random numbers, a comparison unit, the first input of which is connected to the output of the sensor of uniformly distributed random numbers, a memory unit, a first number register, the input of which is connected to the output of the memory unit , characterized in that, in order to improve performance, it is additional. It contains the second register of the number, the first and second address generation blocks, the number switch, the address switch, a synchronization block, the first output of which is connected to the sensor input of evenly distributed random numbers and the first inputs of the first and second address generation blocks, the second - the output is connected to control the inputs of the first register of the number, the address switch and the second block of forming the address, and the third output with the control inputs of the switch of the number, the second register of the number and the first block of forming the address The input of the comparison unit is connected to the output of the number switch, and the output is connected to the second inputs of the first and second address generation units, the outputs of which are connected respectively to the first and second inputs of the address switch, the output of the address switch is connected to the input of the memory unit, the output of which is connected to the input of the second register numbers, outputs of the first and second registers: numbers are connected respectively to the first and second inputs of the number switch. 2 "The device according to π. 1, characterized in that, the address generating unit 'comprises first and second registers, first and second AND elements and a delay element, the input of which is connected to the first input of the first register and is the first input of the block, and the output is connected to the first inputs of the first and second elements,, the second inputs of the first and second elements AND are connected respectively to the second and third inputs of the first register, and the outputs are connected respectively to the first and second inputs of the second register, the group of outputs of which is the output of the block, the group of inputs of of the first register is the second input of the block, and the group of outputs is connected to the group of inputs of the second register, the control inputs of the first and second registers are connected to the control input of the block. >