SU1187162A1 - Device for calculating tangent value - Google Patents

Abstract

A DEVICE FOR CALCULATING THE TANGLES, containing two totalizers, two shift registers, a control unit and an analysis unit, the information inputs of the first and second totalizer-subtractors connected to the direct outputs of the first and second shift registers, the shift control inputs of which are connected to the first output of the control unit The first and second outputs of the analysis unit are connected to the control inputs of the first and second totalizer subtractors, respectively, characterized in that, in order to increase the speed rotates, four groups of elements I are entered into it, and the device start input is connected to the start input of the control unit and the reset inputs of the first and second adders-subtractors, the installation inputs of which are connected to the outputs of the elements And, respectively, of the first and second groups, the first inputs are connected respectively to direct and inverse outputs of the first shift register, the installation input of which is connected to the input of the device variable and the installation input of the second shift register, the outputs of the first and volts The other adders-subtractors are connected respectively to the first and second information inputs of the analysis unit and the first inputs of the AND elements of the third and fourth groups, respectively, whose outputs are connected to the information inputs of the first and second shift registers, respectively, the forward outputs of which are connected respectively to the first and second synchronization inputs adders-subtractors, k /) the second inputs of the elements And of all groups and the output of the readiness of the device, and the control unit contains a pulse generator, two the trigger, the counter, the zero decoder, the three AND elements, the OR element and the four delay elements, the input. The control unit start is connected to the installation input of the counter and through the first delay element to the first input of the first trigger, the direct output and the second input S of which are connected respectively with the first input of the first element And. and the output of the OR element, the first and second inputs of which are connected respectively to the first input of the first element AND and the output of the OR element, the first and second inputs of which are connected respectively to the input of the transition sign of the control unit and the output of the zero decoder, the input of which is connected to the output of the counter, counting input which is connected to the output of the first element And, the second exit of the control unit and through the second

Description

poi delay element - with the first inputs of the second and third elements And, the second inputs of which are connected respectively to the forward and inverse outputs of the second trigger, the first and second inputs of which through the third and fourth delay elements are respectively connected with the inverse output of the first trigger and the output of the second element And, the output of the pulse generator is connected to the second input of the first element And, the outputs of the second and third elements And the inverse output of the first trigger are connected respectively to the third first and the fourth output of the control unit, the analysis unit contains an adder, a comparison circuit, two elements NOT and three modulo-two adders, the first and second inputs of the analysis unit are connected to the corresponding inputs of the comparison circuit 1 2, the output of which is connected to the first input of the first modulo-adder two and through the first element NOT to the third output of the analysis unit, the sign bits of the first and second inputs of which are connected respectively to the first second inputs of the second modulo two, the output of which is connected to the second input p The first modulo-two adder, the output of which is connected to the first input of the third modulo-two adder, the second input and the output of which are connected respectively to the output of the sign of the adder and the input of the second element; the output and input of which are connected respectively to the second and first outputs of the analysis block. a, the third and fourth inputs of which are connected respectively to the first and second inputs of the adder.

The invention relates to computing and can be used in the hardware calculation of elementary functions in digital information pre-processing systems. The purpose of the invention is to increase the speed of interaction. FIG. 1 shows a block diagram of an apparatus for calculating a trigonometric tangent; in fig. 2 and 3 are functional diagrams of the control unit and the analysis unit, respectively; in fig. 4 is a comparison circuit; in fig. 5 and 6 is a diagram of the organization of the reset circuits of adders-subtractors. A device for calculating tangent contains adders-subtractors 1, shift registers 2, groups of IZ elements, analysis block 4, control block 5, start input 6, control block input 7, output 8 of the analysis block, outputs 9–12 of the control block, shift register inputs 13 , inputs 14 adders-seekers, inputs 15 and 16 of the analysis unit, inputs 17 of the elements And, outputs 18 totalizers-subtractors, inputs 19 and 20 of the analysis unit. direct 21 and inverse 22 outputs of the first shift register. Inputs 23 adders-subtractors, outputs 24 and 25 of the analysis block, inputs 26 and 27 of the shift registers. The control unit contains a pulse generator 28, triggers 29, an OR element 30, And 31 elements, delay elements 32, a counter 33 and a decoder 34 .. The analysis block contains a comparison circuit 35, an adder 36, modulo 37 adders, two elements, HE 38, outputs 39 and 40. The comparison circuit contains AND 41 elements and OR elements 42. All subtractors 1, a combination adder 36, comparison circuit 35, branches, And 3 groups, shifting registers 2 contain (n + 3) - bit components, where n is the number of bits of the argument t represented by an unsigned binary number. For input, intermediate and output values, the scale is equal to 2, i.e. The comma is implied to be between the nth and (n + 1) -th bits (numbering is from the least significant to the most significant). The connection between the input entry of the entire device (argument t) and the second inputs of shift registers 2 is made by n-bit buses. Moreover, these connections are made with the offset of tires by one bit in the direction of the higher bits (for the first register 2) rt and two bits in the direction of the lower bits (for the second register 2). In this case, in the second register 2, the inverse bit inputs are used as the second input of the input, i.e. the contents are entered in the reverse code with a minus sign (4 t-2 Communications between the forward 21 and inverse 22 outputs of the first shift register with the inputs of groups of elements I 3 are made with the tires shifted by one bit in the direction of the lower bits. some of them hang in the air, if they are junior, they are connected with a low, zero level (for registers 2 and the first group of elements And 3), or with a high, one level (for the second group of elements And 3). In the event that these are sign buses, then they are connected to the sign source of information. Inputs Reset of both adders-subtractors are connected to the inputs R of some (let's call them j-th) triggers and to the inputs S of the rest (let's call them the i-th) triggers of their accumulative registers. By JM flip-flop all those triggers are assigned the first slug of the second adders-subtractors 1, the numbers of which coincide with the digits of the binary representation in the additional code of the values -2.8452 or -0.0426-2, respectively, of the bits containing zeros. The parameter (duration of the time delay) of the delay element 32 is equal to half the period of the pulse following from the generator 28. The pulse amplitude is equal to high, i.e. unit level, and the duration is less than half of the following period. In the absence of a pulse in the course of the generator, you have a low, corresponding to zero, voltage level. The period of the pulses of the generator 28 must be no less than twice the time of adding the numbers in the sum 11 24 to the subtractor 1 (it is assumed that the shift time of the contents of the shift registers 2 is not more than the time of the addition of the subtractors). All values are presented in an additional code. In the same code all adders work. The operation of the device is based on an iterative algorithm and a series of auxiliary relations qj, sin (Xj., -Yj ,,,) sign (U + 6); ., -qj., a) 2-J; ; ..Y.YJ-, qj., U2; For, 5, where j 1,2, ..., (n + 2) is an iteration number; n argument width t (unsigned); r is the iteration number (), for which X.Yr is within the bit grid, or the number of the last iteration. , -2-, .t - 2.8452, t-0.0426. Г + 1, if 81§пг | -1, if stop at. The operation of the proposed device occurs in two stages: entering the registers with 2 arguments and executing the preliminary calculations of the quantities involved (tx in the iterations, and executing the iterations (for calculating the tangent). Before starting the calculation, the triggers 29 of the control block 5 are reset to 0 (this is done in the end of the previous tangent calculation process, or when the power is turned on.) The value of the argument t (7/4) enters from the outside through the input buses to the input of the first and second shift registers 2, which due to the special bias of the tires due to values of 2t and With the arrival of a signal (a pulse with a positive amplitude, corresponding to a high, single level), the first and second adders-subtractors 1 enter binary values equal to the approximate (n + 3) -discharge representation of the constants -2 , 8452 and -0.0426-2 responsibly, by selectively resetting O or setting these or other triggers of their accumulative registers to 1. These values are then transferred from the outputs of totalizers 1 to the first 15 and second 16 inputs of the analysis unit 4, which determines which one is longer. At the first 24 and second 25 outputs of this block, there appear respectively low and high levels, which, having entered the first and second summators-subtractors 1, switch them to the addition and subtraction mode, respectively. At the same time, with the arrival of the Start signal through the first input 6 into the control block 5 of this signal, the number n + 3 is entered into the subtracting counter 33 (for subsequent counting of the number of iterations). . After some time, the Start signal, arriving at the input of the first trigger 29, sets it to 1, thereby opening the first element I 31. The next impulse from the generator 28 will pass to the second output 10 of block 5 and then to the synchronous inputs 14 of adders-subtractors 1, producing summarization the contents of the first shift register 2 and subtracting the contents of the second, respectively, to the contents of the first and from the contents of the second totalizer-calculators 1. Their new contents will be 2.f- 2.8452 and l / 4t - 0.0042 This same signal from the generator 28 by enrolling in subtractive count chick 33 reduces its contents by one and, after passing through delay element 32 and via the AND gate 31, on Vits third output 11 of the control unit 5. The signal from this output is permissive for mutual rewriting using four groups of IZ elements contained shift registers with the same-name adders and calculators. Moreover, in the summation readers 1, the contents of only the first register 2 are filled up, halved due to the bias of tires in the multi-bit connections between these nodes. Output 22 is inverse, therefore the value t -2 is recorded in the second adder-subtractor 1, while the value t is recorded in the first adder-subtractor. The performance of the permissive process occurs in iterations, i.e. the same in their sequence of actions. The number of iterations (n + 2) {however, they may end earlier if Xf, Yp, in the latter case the number of iterations will be equal to r. One of the iterations is described as follows. The current contents of adders 1 Xj-i and YJ., And the shift registers are fed to inputs 15, 16, 19 and 20, respectively, of the analysis unit, where they are compared using comparison circuit 35, combinational adder 36 and three adders 37 modulo-37 two If the contents of the adders-subtractors are equal, at the second output 40 of the comparison circuit 35, a low voltage level signal that passes through the first element NOT 38 turns into a high level signal and enters the third output 8 of the analysis unit 4. Then it goes to the second input 7 of the control unit 5, where through the OR element 30 it enters the input of the first trigger 29. The latter is reset to O., blocking the further arrival of signals from the oscillator. 28 and sending a high signal from the inverse output to the output-stroke 12. and, via delay element 32, to the input of the second trigger 29, set it to O and prepare the control unit 5 for new tangent determinations. I If the contents of totalizers 1 are not equal, the output 39 of the circuit 35 Comparison using the elements AND 41 and OR 42 produces a high level signal if the number code interpreted as an unsigned number on the first input 15 is greater than on the second 16 This the signal together with the signals from the output of the combinational adder 36 and the output of the second adder 37 modulo two, which shows the signs of the compared numbers, is summed with the help of adders 37 modulo two and goes to the first 24 and through the second element HjE to the second output 25 of the analysis unit 4 . This signal (at output 24) is equal to 1 × 4-1. It controls the operating mode of the first (from output 24) and second (from output 25) adders-subtractors 1. 7 .1 The next pulse from the generator 28 passes through the open first element And 31 to the second output 10 and further to the synchronous input 14 of both adders-1 readers 1. It allows the summation of the contents of the first and second shift registers 2 to the contents of the same-name adders-1 (and since one of them works in the subtraction mode, then Content is summed up from register 2 with a minus sign). The same impulse, passed through delay element 32, flows through element 31, opened by a high signal from the inverse output of the second trigger 29, to the first output 9 of control unit 5 and then to the shift inputs 13 of the two shift registers 2, thereby both registers 2 are halved. Note that the shift is arithmetic, i.e. the sign bit does not move, and the next bit with the sign bit during a shift repeats its value. Thus, the new contents of registers 2 are prepared for the next iteration if it is composed. Each iteration leads to a decrease in the content of the subtracting counter 33. At that moment, when it becomes not equal to zero, the decoder triggers 34 zero, at the output of which a high signal will arrive through the element. ment OR 30, to the input of the first trigger 29, dropping it to zero. This leads to the fact that the supply of pulses from the generator 28 stops, as the first element AND 31 is closed. At the same time, the output of the signal 12 will be a signal of the Ready%, since the tests have ended 2 and the result is ready. The tangent value is at the outputs of the lower-order bits as an unsigned n-bit binary number at scale 2. After the Ready signal, the second trigger is also reset to O using delay element 32, preparing control unit 5 for the next tangent calculation. Stop at the work of the comparison circuit 35 in more detail. If the digits in the higher bits are equal, then the comparison is performed for the next bits, the younger ones, and so on. If some of the bits being compared are not equal, then a signal about this is transmitted in the form of a high-KGB level, if at the first input 15. unit, and on the second 16 is zero, on the first output 39 of the comparison circuit 35. At the same time, the signal 1 from the first element 41 of this bit, passing through the element OR 42 to the next and subsequent lower bits, prohibits the comparison in the other bits. If the numbers are equal in all bits, a low voltage signal will appear on the second step 40. In other cases, output 40 is a high level of voltage supplied through the installation OR from the outputs of either the first or second elements 41. The maximum relative error in the calculation of the tangent depends on the size of the beer best (when) is 0.1%. . The speed is inversely proportional to the width of the item. The average time for calculating a single tangent value is 2. n.-tfsj (tp is the addition time on adder-subtractor 1).

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Claims (1)

A device for calculating a tangent, comprising two totalizers, two shift registers, a control unit and an analysis unit, the information inputs of the first and second adders-subtractors connected to the direct outputs of the first and second shift registers, the shift control inputs of which are connected to the first output of the control unit, the first and second outputs of the analysis unit are connected to the control inputs of the first and second adders-subtracters, respectively, characterized in that, in order to increase the speed Vii, four groups of AND elements are introduced into it, and the start input of the device is connected to the start input of the control unit and the reset inputs of the first and second adders-subtracters, the installation inputs of which are connected to the outputs of the AND elements of the first and second groups, the first inputs of which are connected respectively to direct and inverse outputs of the first shift register, the installation input of which is connected to the input of the job variable of the device and the installation input of the second shift register, the outputs of the first and second sum o-subtractors are connected respectively to the first and second information inputs of the analysis unit and the first inputs of AND elements of the third and fourth groups, respectively, the outputs of which are connected to the information inputs of the first and second shift registers, the direct outputs of which are connected respectively to the first and second inputs of the adder synchronization subtractors, the second inputs of the elements And of all groups and the readiness output of the device, and the control unit contains a pulse generator, two triggers, counter, deshi zero fractor, three AND elements, OR element and four delay elements, input The start of the control unit is connected to the installation input of the counter and through the first delay element to the first input of the first trigger, the direct output and second input of which are connected respectively to the first input of the first AND element. and the output of the OR element, the first and second inputs of which are connected respectively to the first input of the first AND element and the output of the OR element, the first and second inputs of which are connected respectively to the input of the transition sign of the control unit and the output of the zero decoder, the input of which is connected to the output of the counter, a counting input which is connected to the output of the first AND element, the second output of the control unit and through βίο the swarm delay element - to the first inputs of the second and third AND elements, the second inputs of which are connected respectively to direct and inverse outputs of the second trigger, the first and second inputs of which are connected through the third and fourth delay elements respectively to the inverse output of the first trigger and the output of the second element And, the output of the pulse generator is connected to the second input of the first element And, the outputs of the second and third elements And the inverse output the first trigger are connected respectively to the third, first and fourth outputs of the control unit, and the analysis unit contains an adder, a comparison circuit, two NOT elements and three adders according to I’ll remove two, the first and second inputs of the analysis unit are connected to the corresponding inputs of the comparison circuit, the output of which is connected to the first input of the first adder modulo two and through the first element NOT to the third output of the analysis unit, the sign bits of the first and second inputs of which are connected respectively to the first and second inputs of the second adder modulo two, the output of which is connected to the second input of the first adder modulo two, the output of which is connected to the first input of the third adder modulo two, the second input and output of which are connected respectively with the output of the adder sign and the input of the second element NOT; the output and input of which are connected respectively to the second and first outputs of the analysis unit, the third and fourth inputs of which are connected respectively to the first and second inputs of the adder: