SU1049901A1 - Device for computing simple functions - Google Patents

Abstract

A DEVICE FOR CALCULATING ELEMENTARY FUNCTIONS, containing a pulse generator, a key, an argument divider, an argument counter, the first and second summation counters, del-. the approximation plots, the first and second comparison schemes, the first and second reversible section counters, the delay element, the binary multiplier and the reversible result counter, the output of the generator of pulses connected to the information input of the key, the output of which through the argument divider is connected to the counting input of the argument counter The output of which is connected to the prohibitory input of the key, the enabling input of which is connected to the input of the launch of the device, the installation input lOp-, which is connected to the installation ihp-; daMi argument counter and reversible plot and result counters. the output of the approximation plots divider is connected to the counting inputs of the first and second reversible meter counters, the outputs of which are connected to the first inputs of the respective comparison circuits, the outputs and second inputs of which are connected respectively to the installation inputs and outputs of the corresponding summing meters, reverse control inputs of the reverse section and result counters connected to the input of the device mode setting, characterized in that, in order to expand the class of tasks to be performed due to the possibility of effective calculation of functions ± AVn (x tbx + s). and Aolrih Ah. , (The adder-subtractor is entered in it, the control input of which is connected to the device mode setting input, the key output is connected to the divider of the approximation sections and the counting inputs of the first and second summing counters, OUTPUT of the first 4 comparison circuit is connected to the first input of the adder-subtractor , the second input of the COCO of which is connected to the output of the delay element, the input of which is connected to the output of the second comparison circuit, the output of the adder-subtractor is connected to the input of the binary multiplier, the output of which is connected to the counting go reversible counter result.

Description

The corresponding summing counters, the reverse control inputs of the reversible section counters and the result are connected to the device mode job input, an adder-subtractor is added, the control input of which is connected to the device mode job input, the key output is connected to the approximate and counting sections divider input. the inputs of the first and: second summing counters, the output of the first comparison circuit is connected to the first input of the adder-subtractor, the second input of which is connected to the output of the delay element, the input of which is connected to the output of the second comparison circuit, the output of the adder-subtractor is connected to the input of the binary multiplier, you the course of which is connected to the counting input of the reverse result counter. The drawing shows the block diagram of the device. A device for calculating elementary functions comprises a pulse generator 1, a key 2, a divider of 3 approximation plots, a divider 4 arguments, an argument counter 5, a summing counter 6, a comparison circuit 7, a reversible counter of 8 sections, a summing counter 9, a comparison circuit 10, reversible counter 11 plots delay element 12, adder-subtractor 13, binary multiplier AND, reversible counter 15 of the result of input 16-2 of the device; The device works as follows. The initial data is entered through the inputs .: 17 - the initial code in the counter 8; 18 - invoice direction (addition or subtraction) in q4eT4HK 8; 19 - the initial code in the counter 11; 20 - directing the count to counter 11; 21- a sign of the operation (addition or subtraction in the adder-subtractor 13; 22 - the number Q - X (o, is the total number of states of the counter 5 X - the digital analogue of the argument X) in counter 5 (if this number is not entered in the counter, then the device will work in the mode of not calculating, but reproducing up to the exhaustive capabilities of the circuit); -23 - counting direction into counter 15; 2 - initial code into counter 15. After entering the initial data, start command is sent to input 16, key 2 is opened and pulses FROM generator 1 begins to flow to the device nodes. This division.;, divider k reduces the price of a unit of discreteness of the result accumulated in counter 15 At the moment of overflow of counter 5, key 2 closes, and in counter 9 locks the result of calculating the function Y as a digital equivalent. The division factor of divider 3 determines the size of the segment Approximations. As the ratio increases, the size of the approximation area increases. At each approximation area, counters 6 and 9 are cyclically filled to the state of counters 8 and 11 approximation sections and the output signals of circuits 7 and 10 Equals are reset to zero. The triggering times of circuits 7 and 10 are determined by the initial codes in the counters 8 and 11 and their counting directions (addition and subtraction). The pulses from the outputs of circuits 7 and 10, separated in time by the delay element 12, are fed to the subtractor 13. The adder - by the subtractor, depending on the operation entered through the input 21, the addition or subtraction of the pulse sequences arriving at the inputs of the adder-subtractor 13 from the outputs of the comparison circuits 7 and 10 is performed. The resulting sequence of pulses from the output of the subtractor 13 is fed to the input of the linear scaling unit (binary multiplier 14), and from its output to the reversible counter 15 of the result, working either in the summation mode or in the subtraction mode. Thus, a given piecewise linear function is reproduced. When counter 5 overflows, the device stops working and the result counter 15 records the value of the specified function corresponding to the value of the argument entered in the additional code in counter 5. Depending on the initial values and directions of counting entered into the counters 8,11 and 15, as well as the operation specified by the adder 13, the device can reproduce and calculate various elementary functions.

Some of these functions approximate, and some of them model continuous functions. By approximation, we understand the case when the nodal points of a piecewise linear function simultaneously belong to it, as well as an iXexsed continuous function. By modeling is meant the case when the nodal points of the piecewise linear expression function for increments of reproducible and calculated piecewise linear functions in sections. The minus or plus between the members in parentheses indicate the type of operation (subtraction or addition) performed by the adder-subtractor, y.c, (- i -) - a. V) (-1.-- - - am1 ani t п Vm-nw-vn-il (ni.n) (ni-n-l) 01 I l about 1 Ü l nunnn cnR b nifn) (wtn. ((Vn. , fn-M -l. iiY .-- am + (n Vni-ri w-nA-i I () n + m 1 -i ln4-l 1-7.41iY -o, n, f, M .., ,, r 42m-1) n + m Vn-a,} -,

They do not belong to a continuous function, but the nature of these functions is the same, and the structure of the LU increments of the piecewise linear function on its parts corresponds to the structure of the first derivative of the continuous function.

Examples of functions reproduced and calculated by the device are listed in the table.

Approximate and simulated continuous functions 2n-2tY) -1 approximation in X approximation V - С b-x approximation in approximation Lx approximation Y “A1p (x-, 0 modeling UZ-A1p (x-Bx + c) modeling (x2 + x) modeling (xibx + c) modeling y xArthAx

The list of Vos-55 functions given in the table .J-lp will be increased. Functional and computable device capabilities of the proposed

the whole of piecewise linear functions and approximate devices are much wider than those of simulated and simulated continuous known ones.

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Claims (1)

DEVICE FOR CALCULATION OF ELEMENTARY FUNCTIONS, containing 'pulse generator, key, argument divider, argument counter, first and second totalizing counters. Approximation section divider, first and second comparison schemes, first and second reversible section counters, delay element, binary multiplier and reversible counter a result counter, wherein the output of the pulse generator is connected to the information input of the key, the output of which through the argument divider is connected to the counting input of the argument counter, the output of which is connected to by a prohibiting input of a key, the allowing input of which is connected to the start-up input of the device, the installation input of which is connected to the installation inputs of the argument counter and the reverse part and result counters, I; ; ”The output of the divider of the approximation sections is connected to the counting inputs of the first and second reversible counters of the sections, the outputs of which are connected to the first inputs of the respective comparison circuits, the outputs and second inputs of which are connected respectively to the installation inputs and outputs of the corresponding summing counters, the inputs for reversing the control of the reversing section counters and the result are connected to the input of the job mode of the device, characterized in that, in order to expand the class of tasks at the expense of the possibility of additional th calculation functions AEn ± (x ² + bx + c). and Aar th Αχ. , the adder-subtracter is introduced into it, the control input of which is connected to the input of the device mode setting, the key output is connected to the input of the divider of the approximation sections and the counting inputs of the first and second totalizing counters, the output of the first comparison circuit • is connected to the first input of the adder-subtractor, the second the input of which is connected to the output of the delay element, the input of which is connected to the output of the second comparison circuit, the output of the adder-subtractor is connected to the input of the binary multiplier, the output of which is connected to the counting input of the reverse explicit result counter. SU. „, 1049901