SU1170461A1 - Calculating device - Google Patents

Abstract

A COMPUTING DEVICE containing a pulse generator, a key, an operation mode switch, a binary counter, a code comparison circuit, an accumulator, a subtraction counter, an argument register and an OR element, the output of the pulse generator is connected to the information input of the key whose output is connected to the input of the operation mode switch , characterized in that, in order to expand the scope of application by calculating the additional function of

Description

The invention relates to computing and can be used in hardware computing units or functions of specialized computers, linearizing devices. The purpose of the invention is to simplify the device, increase speed and expand the scope of application for calculating the additional function ((1-еЬ. Figure 1 shows a block diagram of the computing device in Fig. Implementation of the subtractor. The device (Fig. 1) contains a pulse generator 1 , key 2, accumulating adder 3, switch 4 operating modes with outputs 5 and 6, subtractor 7 with inputs 8 and 9 and output 10, counter-11, delay element 12 deducting counter 13, element OR 14, binary counter 15, circuit 16 code comparison, register 17 argument. The pulse subtractor (Fig. 2) contains the Dr-trigger 18 and the element OR 19. The operation of the pulse subtractor 7 is illustrated in detail in the time diagrams (Fig. 2). The device for calculating the operation works as follows. on the cumulative adder 3, t is recorded in subtractive counter 13, 1 is recorded, memory counter 11 and binary counter 15 are in the zero state, and in the register 17 of the argument the number P is written. Since the binary counter 15 is in the zero state, and in the register 1 of the argument the number is written, the output of the code comparison circuit 16 is a logic level 1 that permits the passage of pulses from the generator 1 of the reference frequency pulses through the key 2 to the clock input of the accumulating adder 3 and through the key 2 to the counting input of the deducting counter V The first pulse received from the pulse generator 1 to the clock input of the accumulating accumulator 3, sends to the contents of the accumulating accumulator 3 the contents of the counter 11. As in the accumulating accumulator e 3 is recorded 1, and in counter 11 of memory O, then, consequently, the ratio of accumulating adder 3 remains the same, i.e. equal to one. This corresponds to 1. The same first pulse from the generator 1 of pulses through the key 2 and the switch 4 is fed to the counting input of the deduction counter 13, in which it is written. At the zero output of the subtracting counter 13, a short pulse appears that goes through the OR element 14 to the input of the binary counter 15, increasing its contents by 1, and to the recording input of the counter 11, rewriting the contents of the accumulating adder 3 to this counter, i.e. 1, and through the element 12 of the entry delay of the entry of the subtracting counter 13, rewriting the contents of the binary counter 15 into it, i.e. 1. The second pulse from the pulse generator 1, arriving at the clock input of the accumulator of the adder 3, adds to the contents of the accumulating adder 3 the contents of the counter 11. Since the accumulating summat3 is recorded 1, and 11 11 is recorded in the recorded II, then f is sequentially accumulator 3 will be equal to 2, corresponding to 2. This same pulse subtracts 1 from counter 13. Counter 13 will zero again and with the pulse from its zero output will copy the contents of accumulator 3, i.e. the number 2 adds 1 to the binary counter 15 and through the delay element 12 rewrites from the binary counter 15 to the subtracting counter 13 the number 2. The third pulse from the pulse generator 1 summarizes the number 2 in accumulator 3 with the number 2 in counter 11, the result will be equal to 4. This same pulse reduces by 1 the contents of the counter 13, i.e. the number 1 remains in this counter. The fourth pulse from generator 1 summarizes., number 4 in accumulator 3 with number 2 in counter 11 and records a result equal to 6, corresponding to 3. This same fourth pulse subtracts 13 units from the subtracting counter, and counter 13 flushes with a pulse from the output of zeroing, rewrites the number 6 from accumulating adder 3 to counter 11, adds one to binary counter 15, after which the number 3 will be written in it, and through delay element 12 rewrites the number 3 of the binary counter 15 to the subtracting counter IC 13. Next, the device works in a similar way. Each pulse from pulse generator 1 adds the contents of counter 11 to the contents of accumulating adder 3 and subtracts one from subtracting counter 13. In the event that counter 13 is zeroed, the pulse from its zero output rewrites the number from accumulator 3 to counter 11, adds 1 to binary counter 15 and, via delay element 12, writes the contents of binary counter 15 to subtractive counter 13.

The calculation process continues until those numbers until the number in the binary counter 15 becomes equal to the number P recorded in the register 17 of the argument. At this time, the output of the code comparison circuit 16 is O, which closes the key 2, prohibiting the passage of pulses o generator 1 pulses. When calculating the function ij (the 1st device works by following the image. Switch 4 is in Step 5. The accumulating adder 3 and the counter 11 are in the zero state, the number 17 in the argument register 17 is written. Since the binary counter 15 is in the zero state, and in the register 17 of the argument the number p is written, then the output of the circuit 16 of the comparison of codes is the logic level 1, allowing the passage of the pulse sequence X from the generator 1 of the reference frequency pulses through the key 2 to the clock input of the accumulating adder 3, to the binary counter 15 hours Element OR 14 and input 8 of subtractor 7. The increment dx of the pulse sequence x arriving at the clock input of accumulating adder 3, from the overflow output, which increments dz of the pulse sequence z is received, taking into account that the outputs of counter 1

dy dx-dz (2)

From (1) and (2) we get

, (3)

dy dx

ah

Integrating (3) taking into account the limits of integration, we obtain the value of y in the counter 11 L 14 11, the code of the current value y is formed, we can write where a 2 is the coefficient of the counter recalculation 11 W is the number of bits. The pulse sequence r from the overflow output of accumulating adder 3 enters input 9 of subtractor 7. The pulse sequence U from output 10 of subtractor 7 enters input of counter 11. The increment dy of the pulse sequence y is determined by the difference of the increments dx and dz of the pulse sequences X and Z, respectively. (, .-) The calculation process continues until the number in the binary counter 15 becomes equal to the number n written in register 17 of the argument. At this point in time, the output of circuit 16 of code comparison is O, which closes key 2, prohibiting the passage of pulses from pulse generator 1. The proposed device calculates the function and j with lower hardware costs and with much greater speed compared to the prototype, since in the proposed device the calculation is performed directly, in one work cycle, and in the prototype the calculation process is carried out in several cycles. In addition, the introduction into the device of the indicated nodes and the change in the connections allows one to additionally calculate a function of the form a (, - e).

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Claims (1)

A COMPUTER DEVICE comprising a pulse generator, a key, an operating mode switch, a binary counter, a code comparison circuit, an accumulating adder, a subtracting counter, an argument register, and an OR element, the pulse generator output being connected to the key information input, the output of which is connected to the mode switch input work, characterized in that, in order to expand the scope by calculating the additional function y = (1, -ea), a subtractor, counter and delay element are introduced into it, and the output of the connection key connected to the clock input of the accumulating adder, the information outputs of which are connected to the information inputs of the counter, the information outputs of which are connected to the information inputs of the accumulating adder, the overflow output of which is connected to the first information input, the subtractor, the output of which is connected to the counting input of the counter, the first output of the switch operating mode is connected to the second information input of the subtractor and to the first input of the OR element, the output of which is connected to the information input of the binary about the counter, the information outputs of which are connected to the information inputs of the subtracting counter and to the first group of information inputs of the code comparison circuit, the second output of the operation mode switch is connected to the counting input of the subtracting counter, the zeroing output of which is connected to the counter recording input, the second input of the OR element, and through the element delays with the input of the subtractive counter record, the outputs of the argument register are connected to the second group of information inputs of the code comparison circuit, the output of which is connected to the control key stroke.