SU1290305A1 - Device for calculating function value - Google Patents

Abstract

The invention relates to the field of computing and can be used as a functional real-time converter. The aim of the invention is to increase the accuracy of reproducing the values of a function for a given amount of memory by increasing the number of node points by the value of the function. The device for calculating the functions. contains 1 interval counter, decoder 2, first encoder 3, function increment memory block 4, first buffer register 5, first adder 6, first iteration register 7, result register 8, control block 9, second encoder 10, memory block II the increments of the argument, the second buffer register 12, the second summator 13, the second register 14 of iteration, the counter 15 of the address. In blocks 4 and 11 of the memory, fundamentally different values of the function and argument increments are stored. The function value is restored by summing the increment values and the previous value of the function. 5 il. (LE 21 about SD

Description

The invention relates to computing and can be used in information-measuring and control systems when performing functional transformations in real time.

The purpose of the invention is to increase the accuracy of reproduction of a function for a given amount of memory by increasing the number of nodal points of the function values.

Figure 1 shows the functional diagram of the device for calculating a function; Fig. 2 shows an algorithm for operating the device; FIG. 3 is a control block diagram; 4 is a clock node diagram; FIG. 3 is an example of setting the function Y F (x).

S - values of constant increments, which correspond to the increment of addresses В, V.,. .

В „(g 9,

); q. - difference increments funk10

on the i-th and i-1st interval, i.e. q. S, - b,; increment of addresses when changing b; RJ is the difference between the increments of addresses on the i-th and i-1st interval, i.e. R, - (d).

These numbers are i in, m-l,. . . , 2,1, 0 are the contents of the interval 1 counter, and when going to a new interval / control unit 9, it outputs a unit subtraction signal from the contents of the interval 1 counter. The values of R ;, the contents of block 11 of the memory of the argument arrays, the address for this block of memory being the unitary code (the serial number of the Device for calculating the function 20 1, obtained after the decoder 2). contains interval 1 counter, decrypt- To reduce the volume of block 11, memory 5

RATOR 2, first address encoder 3., function increment memory block 4, first buffer register 5, first adder 6, first iteration register 7, result register 8, control block 9, second address encoder 10 block of argument increment memory 11 , the second buffer register 12, the second adder 13, the second register 14 iteration, the counter 15 addresses.

The control unit 9 contains the first 16 and second 17 inputs of the clock mode setting, the first 18 and second 19 inputs of the argument increment mode setting, the start input 20, the delay element 2, the pulse generator 22, the control encoder 23, the first status register 24, the group of AND elements 25, the second state register 26, the control decoder 27, the clocking node 28, the second 29 and the first 30 elements OR, the first 31 and the second 32 triggers ,. the second 33 and the first 34 elements I.

The node 28 clocking contains the first 35 and second 36 elements OR,

the first 37 and the second 38 AND, the third 39 and the fourth 40 elements And 41, the sixth 42, the seventh 43, the eighth 44 elements AND, the third 45 and the fourth 46 elements OR, the first 47 and second 48 elements NOT.

The device operates as follows.

Lig.5 presents an example of the graph of the reproduced function y, F (x), where denoted: S ,, b

S - values of constant increments, which correspond to the increment of addresses В, V.,. .

В „(g 9,

); q. - the difference between the increments of the function

These argument increments store only the various Rs; (not equal to each other, therefore, the outputs of the decoder 2, addressed to the same value V., are combined by the second encoder lO.

Similarly, in block 4 of the function increment memory, different values of the functions are stored from the increments of functions 8, ,, S.- -. &Amp; h. T-q, 5,,

i q.

q, - & Л 3 3 -5,., q,.-i, Although the law of changing address increments and changing a given function is determined by the form of the function F (x) itself, the magnitude of the change in the value of the function and the change in address is almost always not. Coincidences can be sticky in those areas where the derivative of the function is equal to the value of the argument address change), so the outputs of the decoder 2 by the first encoder 3 are combined according to their own rule, generally excellent. from the rule of the second encoder 10 for a given real-time function. I

The operation of the device is carried out in a strict algorithmic sequence (figure 2). After the Start-up signal, control unit 9 sets all registers Pr 5,7,8,12 and 14 and counters Sch1, Sch15 to the initial (zero) State (operator A). Then from

about

the numerical block 4 of the function increment memory is used to match the contents of the zero address (operator AI and write to counter 1. The zero address of the function increment memory 4 stores the increased number of function intervals F (x) by 1, and the zero address of the memory block 11 increments of the argument — the initial value y, the kotoroe, is sent to the result register 8 (operator Ajj. Next, the contents of the address counter 15 are checked. If the content of Cr15 is zero (this is only at the beginning of the work or at the end of the next interval F ( x) then the interval 1 is subtracted from the contents of counter 1 (operator A and parallel matching from memory blocks 4 and 11 with the corresponding output of q and R. to buffer registers 5 and 12, and then also Pr2 + Pr7 and Prg12 + + Prg14 and results of Pr7 and Prg14 (operators A ,, - A ,, and A - A Contains Prg1 4 (the number of samples in this i-th interval) is recorded in, after which a check is made, whether the request for issuing the next value of F (x) (operator A. s ;. If the request is received, the calculation of the value of y is +5; (the operator counter value, which stores the number of samples in the ij-th interval, decreases by 1: (Cf15-1) and the second trigger of control block 9 is reset to the zero state ((operator A, after which the entire algorithm repeats itself from checking the contents of the counter 15 address.

The proposed device can operate both with internal and not external clocking due to the presence of special inputs 16 and 17. When working with internal clocking, signal 1 is not fed to the input, therefore, the first trigger 31 of the control device remains in the zero state and the operation of the control unit is performed by an algorithm with a direct transition from state aj to state a. If the device for calculating clocks is intended to be used with external clocking, a command to set the first trigger 31 of the control unit to state I is given to the start command at input 17. In the latter case, the device can operate with variable

interval f step calculation v The control device has an additional input 16 for external reset of the first trigger 31 in O (internal reset by the operator automatically at the end of work, A j,), which allows using inputs 16, 17 and 19 to work also in external start mode , pause and continue counting with automatic clocking, starting from any intermediate point of the value of F (x),

The function calculation device operates in accordance with the algorithm (Fig. 2), according to which control unit 9 is waiting for an external clock signal (in this case, a time stamp, the arrival frequency of which can be several orders of magnitude lower than the clock frequency of the control unit) getting it from the counter of address 15 is subtracted I. If this is done within the i-ro interval (the contents of the counter are non-zero), then increment q is calculated, its algebraic addition (add or subtracting with the previous function value, stored in the first register 7 iteration, and writing the obtained value to the result register 8. In the case of the end of the i-th interval, simultaneously with the process of finding the function value, the next i + 1-th For this, operations are also performed as for V with the argument increment memory block, the second adder 13 and the second iteration register 14, after which the new interval value in the parallel code is written to the address counter 15, and from the counter 1 intervals subtract 1 for varying the slot number. The control unit then produces -v with npoBepKaj whether the end signal is not wired and whether the end signal is a sign of the completion of the program for calculating all function values, then the initial setting of the external clock trigger is made. If the signal is an external signal, the device goes into the next standby mode signal arrival / lx, retaining the contents of all memory registers and counters.

five

The control unit 9 operates in the following sequence. By the Start signal, the first and second status registers are set to the initial (zero) state, the generator 22 pulses are started through a delay. The first signal of the pulse generator 22 interrogates the control decoder 27, and the clocking node 28 forms the corresponding control A. and the transition signal of the control unit from zero to the next state is in full accordance with the algorithm. The next time pulse T is used to rewrite a (t - (- l) to a (t), i.e. from Pr24 the contents are transferred to Pr26 The second pulse T of the generator repeats the procedure of the control unit from the first state already.

In FIG. 3, the following notation is introduced:

T, lx - flip-flops with code inputs for setting the feature External clocking (T) and input

dx B51 of another measure of the next change; , T, is a synchronous pair of pulses that are shifted in time in such a way that it is for the same time point tt (t) rt, lg (t) 0;

a (t), are the states of the control 9 block a (t + l) of laziness and the present and subsequent t + 1 main (t) time tick; Hell, A, block output commands

BUT,

.

 9

management;

Pr a (t) and four-bit registries Pr a (t + .l) ry;

t a; - outputs of the decoder.

A block of eight two-input elements And is used to rewrite the contents of Pr a (t + 1) into Pr a (t)., And the encoder to convert the unitary (a, a ,, .., av) status code of control block 9 into binary positional status code a (t + l).

The device can have various versions, in particular, for calculating increments instead of registers, and adders can be used with a microprocessor.90305-6

Claims (1)

Invention Formula A device for calculating a function, -containing a decoder, first г address encoder, function increment memory block, first buffer register ,, first adder, first iteration register and result register, with the decoder output connected to JQ input of the first address encoder, the output of which is connected to the address input of the incremental memory block; the output of which is connected to the information input of the first buffer re-; 15 of the horn 3, the output of which is connected to the input of the first term of the first adder, the output of which is connected to the information inputs of the first register of iteration and the result register, the output of which is the output of the device function value, the output of the first iteration register connected to the input of the second addend of the first adder, different 25 in order to increase the accuracy of the reproduction of a function for a given amount of memory by increasing the number of nodal points of the function values, a counter is entered in it for 30 intervals, an address counter, an argument increment memory block, a second address encoder, a second buffer register , second adder, second iteration register and control block, j, the output of the first buffer register is connected to the information input of the interval counter, the output of which is connected to the input of the decoder, the output of which is connected to the input of the second address coder, the output of which is connected to the address input of the memory of apryi ieHTa, which is connected to the information - by the second input of the second buffer register 45, the output of which is connected to the information input of the result register and the input of the first term of the adder, the output of which is connected to the information input 50 of the second iteration register, the output of which is connected to the input of the second term of the second adder and the informational input of the address counter, whose code is connected to the input 55 enabling the calculations in the interval of the control unit whose stop input is connected to the output of the counter j intervals, the device start input is connected to the one-input input of the block control, the first and second inputs of the device clock setting mode are connected to the same inputs of the control unit, the first and second inputs of the device argument increment mode setting are connected to the same inputs of the control unit, the first clock output of the control unit is connected to the reset inputs of the interval counter, address counter, first and the second buffer registers, the first and second iteration registers, and the result register; the second clock output of the control unit is connected to the write enable input of the integer counter shafts, the third clock output control unit is connected to the write enable input of result register, the fourth tak tovy output is connected to strobiruyush, br input of the first register iterations fifth clock output control unit connected to the input. the subtraction of the address counter, the sixth clock output of the control unit is connected to the subtraction input of the interval counter, the seventh and eighth clock outputs of the control unit are connected to the gate inputs of the first and second buffer registers, respectively; the ninth and tenth clock outputs of the control unit are connected to the gate inputs of the first and second respectively The second cy p-atop eleven and the twelfth clock outputs of the control unit are connected to the recording resolution inputs of the first and second registers respectively. and, the thirteenth clock output of the control unit is connected to the write enable input of the address counter, the control unit contains two status registers, a control decoder, a control encoder, a group of AND elements, a delay element, a pulse generator, two OR elements, two AND elements , two triggers, and a clocking node containing four OR elements, eight AND elements and two NOT elements, the control input start input is connected to the reset inputs of the first and second status registers and, through the delay element, to the start input pulse generator, the first output of which is connected to the strobe input of the control decoder, the output of the reset feature of the device  , 2903058 which is connected to the first clock output of the control unit, the first and second outputs of the initial setting of the control decoder are connected to the second and third clock outputs of the control unit respectively, the output of the permission of the calculations on the interval of the control decoder is connected to the first 10 by the input of the first element OR of the clocking node, the output of the external clocking characteristic of the control decoder is connected to the first input of the second element., OR of the clocking node, the output is a sign of variable increment increments control decoder is connected to first inputs of the first and second  elements and clocking node, output Sign of permission of calculations on 20 interval control decoder connected to the second input of the first clock unit RSH element; the output of the sign of stopping the computation of the control decoder is connected to the first  the input of the third element And and with the first input of the fourth element And the clocking node, the output of the characteristic of the external clocking of the control decoder is connected to the second input 30 of the second element of the RSH of the clock node; NIN, the output of the first element OR node; clocking is connected to the first inputs of the fifth and sixth elements AND of this node, the second input of the fifth element AND of the clocking node is connected through the first element NOT of this node to the output of the first element AND of the control unit and the second input of the sixth element And clocking node, output 40 of the second element OR of the clock unit is connected to the first inputs of the seventh and eighth elements AND of this node, the second inputs of the seventh and eighth elements And are connected respectively to the direct and inverse outputs of the first trigger of the control unit, the second inputs of the first and second elements And the node of the timing are respectively connected to direct and inverse outputs of the second trigger of the control unit, the outputs of the seventh and eighth elements AND of the clock unit are connected to the first inputs of the third and fourth elements OR 55 of this node, respectively, the second inputs of the third and fourth elements of the clocking node OR are connected. respectively with the outputs of the eighth 45 at 1 and the ninth elements AND of this node, the second input of the third element And the clocking node is connected through the second element NOT of this node to the second input of the fourth element AND of this node and the output of the second element AND control unit, the outputs of the fourth element OR and the fourth element And clocking node are connected respectively with the first inputs of the first and second elements OR of the control unit, the outputs of the fifth element AND, the sixth element AND, the third OR, the fourth element OR, the third element AND, the fourth element AND the clock unit connected to the outputs of the control encoder, the outputs of which are connected to the information inputs of the first state register, the outputs of the bits of which are connected to the first inputs of the corresponding elements of the And group, the second inputs of which are combined and connected to the second output of the pulse generator, the outputs of the elements And 90305 the groups are connected to the information inputs of the second state register, the output of which is connected to the input of the control decoder, the first and second inputs of the timing mode setting of the control unit are connected to the second input of the second OR element of the control unit and the reset input of the first trigger of the control unit respectively, the first and second the control unit mode control inputs are connected to the second input of the first element OR and the reset input of the second trigger of the control unit, respectively; J5 calculation resolution input per interval e and the stop input of the control unit connected to the inputs of the first and second elements AND of the control unit, respectively, from the first to the third and third outputs of the control decoder are connected to the first to thirteen clock outputs of the control unit and to the first to thirteen inputs control encoder. 25 Cns rg n AoAi ... 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