SU711562A1 - Exponentiating arrangement - Google Patents

Description

: 54) DEVICE FOR POTENTIALING LOGARIFMS

(The cops And of the first group are connected to the output of the delay element, the input of which is connected to the output of the first element And, one of the inputs of which is connected to the input bus, moreover, the zero input of the trigger is connected to the installation bus to which the reset input of the counter 2 is connected. A disadvantage of the known device The fact is that the calculated values of the potentiation results for twenty-bit binary codes of logarithms of numbers in some cases differ from their true values from the third digit.

The aim of the invention is to increase the accuracy of the device for potentiating logarithms.

This is achieved by the fact that in the device for potentiation, containing a counter, shift register and trigger, the first inputs of which are connected to the installation input of the device, the output of the trigger is connected to the first inputs of the AND elements of the first group and through the first delay element to the first inputs of the AND elements of the second group and the first input of the first element And, through. which the clock input of the device is connected to the input of the block of shift registers, the outputs of which are connected to the second inputs of the corresponding elements And the second group, the third inputs cat The first and second inputs of elements AND of the first group are connected to the corresponding outputs of the detector, whose inputs are connected with the outputs of the shift register, the outputs of elements AND, the second group through the first element OR are connected to the input of the adder, the outputs of the elements AND of the first group are connected to the inputs of the second group element OR, the output of which is connected to the corresponding input of the adder, the first distributor, whose input is connected to the control input of the device, the second element AND, two elements AND And, the element YE, two distributors, three elements OR element OR NOT, four elements AND, Two delay elements are introduced, and the output of the first distributor is connected to the input of the second distributor, the output of which through the third element OR is connected to the inputs of the second and third elements AND , the output of the third element AND is connected to the second input of the clock and through the second delay element to the input of the third element OR, the counter outputs through the series-connected element OR-NOT, the second element AND and the element are NOT connected to the input of the third element And that, the output of the second AND gate connected in series through the third valve and a fourth OR gate connected to the fourth AND gate platoon through which the output of the adder coe

device with the output, periam group of outputs of the first distributor through the fifth element OR is connected to the input of the fifth element AND, the second group of outputs of the first distributor through the sixth element OR is connected to the input of the fifth element OR and the second input of the shift register, group of outputs of the second the distributor through the seventh element OR is connected to the third input cm of the counter and through the sixth element I to the fourth input of the counter, one of the outputs of the group of the second distributor is connected to the second trigger input, the information input is roystva connected to the input of the sixth AND gate and via a fifth element and the third input of the shift register and the input of the third delay element whose output is connected to third inputs of AND gates of the first group.

The drawing shows a block diagram of the device.

The device contains valves 1, 2 ,. 3, counter 4, shift register 5, shift register block b, decoder 7, trigger 8, adder 9, group of nodes 10 specifying coefficients, group of elements AND 11, group of elements AND 12, elements OR 13-19, elements And 20-25 , element OR NOT 26, elements 27-29, element NOT 30.

The operation of the device for potentiating the logarithms of binary numbers is carried out as follows. In the initial state, the counter 4, the trigger 8 and the register 5 are set to the zero state. In the first cycle, a unit is fed to the distributor 1 at the control input. At the same time, starting from the first clock cycle, the information input is first fed to the mantissa of the logarithm with low-order bits, and then the characteristic is also given with low-order bits. From the first to the sixteenth clock cycles, from the output of the element OR 17, a unit is output, which is fed to the element AND 24. As a result, the mantissa of the logarithm is recorded in the element 29. The logical levels of the last four bits of the mantissa of the logarithm are entered into shift register 5, since one is fed to it from the element OR 18 from the thirteenth to the sixteenth clock cycles. As a result, a unit is formed at one of the outputs of the decoder 7, which is fed to one of the elements 11 and one of the elements 12 12. At the seventeenth clock cycle, the signal from the corresponding output of the distributor 2 triggers 8 into one state, and thereby unlocks the elements And 11. As a result, the binary code of the mantissa of the logarithm from element 29 through the selected element And 11 is passed to the input of the corresponding node 10. A unit from the output of trigger 8 through element 27, the delay time of which is equal to the operating time of nodes 10, opens the And 20, thus allowing the passage of clock pulses to block 6. Through selected elements AND 12 and element OR 13, information from the corresponding register of block 6 is fed to one of the inputs of adder 9, to the other input of which through element OR 14, information is output from the output of the selected node 10. At the output of the adder 9, a binary number mantissa is formed according to the following system of equations:

xy + o, 01001010.110y + 0.101101010011, 01000010101y + 0.101111001101 Hd y + 0.00111010010y + 0.110001000010, 0011000IOOu + 0.110010110100 X5 y + 0.00101000011y + 0.110100100001 Xj, y + 0,00011110101y01 + 0.110110001010, 00010100111у + 0.110111101110 xg; y + 0 00001010011y + 0.111001001100

“9 - at + 0.111010011111 ,, 1.00001011111y + 0.111000110101 x 1.00010111101y + 0.110110111111 1.00100100001y + 0.110100110101 1.00110001000y + 0.110010011011. 1.00111110100 + 0.101111101011 1.01001100101y + 0.10110.0100101 1.01011011010y + 0.101001001010

The first two terms of the equations to, -Xg and the first members of the equations are formed in nodes 10, and the third members of the equations and the second members of equations Xd-x are written in the registers of block 6. At that, each node 10 corresponds to one of the registers of block 6. From the seventeenth to the twentieth clocks at the output of the element OR 19, a unit is formed, which through the element 25 permits recording of the logarithm characteristic into counter 4. At the twenty-eighth clock cycle from the output of the distributor 2, the unit is fed to the input of the element OR 15. If at least one counter of the counter 4 records one then on the output of the element And 21 is generated zero level, which through the element NOT 30 is fed to the input of the element And 22. The unit from the output of the element And 22 is fed to the input of the counter 4 and there is a decrease in the content of the counter 4 by one. The unit from the output of the element AND 22 through the element 28 at the subsequent cycle is fed to the input of the element OR 15. The described cycle repeats until the contents of counter 4 are zeroed out. In this case, the output of the element 21 makes a single level, which starts the distributor 3, and a single level is generated at the output of the OR element 16, which unlocks the AND 23 element and the formation of the binary code of the desired number begins at the device output.

The invention achieves an increase in the calculation accuracy by comparing

with a prototype in four orders, since in a known device, the calculated values of the potentiation results for sixteen-bit binary mantis codes of logarithms in some cases differ from their true values from the third bit, and in the fourth, from the fourteenth.

According to the proposed publication, a technical project approved by the USSR Ministry of Instrument has been developed. According to the plan of the USSR Minpribor, the proposed device for potentiating logarithms will be introduced for the first time at the NPO Elva enterprise in 1978-1979. as part of a micro-computer and a tunable control logic machine. The economic effect that can be obtained by the national economy as a result of using the proposed invention in the mass production of these computers per year in an amount of 100 pieces each will be about 65 thousand rubles. in year.

Claims (1)

Invention Formula A device for potentiating lagriphms containing a counter, a shift register and a trigger, the first inputs of which are connected to the installation input of the device, the output of the trigger is connected to the singing inputs of the elements of the first group and through the first delay element to the first inputs of the elements of the second group and the firstBgm input of the first element: ment And, through which the clocking input of the device is connected to the input of the shift register unit, the outputs of which are connected to the second inputs of the corresponding elements And the second, group, the third inputs of which and the second input The elements of the AND elements of the first group are connected to the corresponding outputs of the decoder, the inputs of which are connected to the outputs of the shift register, the outputs of the elements AND of the second group through the first element OR are connected to the input of the adder, the outputs of the elements AND of the first group are connected to the inputs of the second element OR , the output of which is connected to the corresponding input of the adder, the first distributor, the input of which is connected to the control input of the device, the second element is AND, two elements OR, the element is NOT, is this In order to increase the accuracy, two distributors, three OR elements, an OR-NOT element, four AND elements, two delay elements are entered into it, and the output of the first distributor is connected to the input of the second distributor, the output of which is through the third OR element connected to the inputs of the second and third elements And, the output of the third element And connected to the second input of the counter and through the second ele,