SU1411727A2 - Device for preprocessing of information - Google Patents

Abstract

The invention relates to the field of computer technology and can be used in debugging, testing and testing process control systems, as well as in the composition of various types of simulators and simulators working in conjunction with computers. The aim of the invention is to expand the field of application of the device by forming the state of the number of pulse sensors. Two meter blocks, a register block and a divider are entered into the device. This allows one to form additional information on the state of the number of pulse sensors and transmit it on request to the computer along with information on the status of analog sensors. I il.

Description

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with:

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The invention relates to computing technology, can be used during debugging, testing and testing of process control systems, as well as in various types of simulators and simulators working in conjunction with computer; improvement of the device according to the author. St. No. 1062684.

I The purpose of the invention is to expand the use of the device by fsming the state of the number of pulse sensors.

i The drawing shows the functional 1

u device diagram.

I The device contains an input block 1, a buffer memory block 2, a memory block 3. ti, counter 4 times, arithmetic unit 5, encoder 6, element 7 back (rzhki, switch 8, divider 9, block 10 registers, the first 11 and second 12 blocks of counters, inputs and vyho- 13-17.

I The device works as follows.

The principle of operation of the device is based on the calculation of H1 at the time when requests from a computer arrive, either of the value of the reproduced analog signal at the interpolation segment given by the codes of its beginning, end and duration, or the formation of the state of the reproduced number-pulse signal of the even distribution of the specified number pulses at a given time interval and issuing a request signal to a computer when one short circuit overflows the number-pulse signal-jioB counters. The distribution of production pulses by determining the minimum time of 41 changes given

The values of K-on the time interval D-And the divider and the implementation of a single

1 |: the reading of the sensor number-pulse-rtoro in a block of 12 counters f using the time period ut 1 in a block of 1 1 counters.

The number of conversion channels AND depends only on the amount of memory used by the memory, as well as the size of the fractioner and the switch that determines the addressing capabilities,

At each moment in time, the device stores information of two frames {current and subsequent. Each 1sadr b contains the coefficients k (jl, N), which determine the values of analog signals at interpol 1 nodes or the values of the change of the pulse number at a given time interval and the value of the interpolation interval time, common for all conversion channels 5 and an array of time values that determine the delay in issuing information for each channel, corresponding to the time of information passing through the system of communication devices with the object.

After the interpolation interval of the current frame has elapsed, the time of the subsequent frame begins, and information for the new frame is entered into the device, and this information is updated regardless of the presence or absence of requests from the PMA.

At the initial moment of time, input and recording is performed in block 2

a buffer memory of coefficient values for all the conversion channels and the corresponding delay values. This information is then rewritten into memory block 3, and e buffer buffer block 2 is recorded as new.

ki information frame || , hence the values

KL

AnaO 0 determining state

five

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log sensors are rewritten into memory block 3} and the values of kM, which determine the change in the number of pulsed signals 5 together with the value of the interpolation interval, are alternately fed to the input of the divider 9. The divisor op S determines the value of t -t- at least 1

The first time the state of the number of pulsed signal changes for each channel that is written to the corresponding register of the register block 50 and the time counter of the block 1i.

From the moment the device starts up, each time counter starts counting a predetermined time, after which the end-of-count signal causes the corresponding NUM counter of block 12 to increase the current value of the pulse number signal by 1. The same signal goes to the control input of the corresponding register of block 10 by allowing the ut value to be rewritten at the appropriate time counter of block 11 for continued operation. If one of the counters on the control output overflows, the device31

The computer receives a chpros signal on the computer, after which the state of the counter can be read through the switch 8 by issuing the corresponding command to the input of the encoder 6.

The value of the interpolation interval f is entered in the arithmetic unit 5 and the counter 4 times. The information for the second frame, i.e. coefficients

1 K; S of all channels conversion I Z J 1

the corresponding delay values and the interpolation interval value L of the second frame are in block 2

buffer memory.

When a request from a computer arrives at the control input 16, the encoder 6 generates a code arriving at the memory block 3 as the address of the coefficients K and k1 of the values 1-1 1

govogo signal, and the control input of the switch 8 - as the address of the input information in the EVM.-

The values of the coefficients selected at the addresses formed by the encoder 6, from the output of the memory block 3 are fed to the arithmetic unit 5. The latter, by the obtained values of the coefficients K. and -, the value of And, and

the value of the current time t on the interpolation interval., coming from the counter 4 of time, determines the value of the analog signal at the time of the survey as a code

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which comes from the output of block 5, to the first information input of the switch 8.

From the second output of the memory block 3 and the input of the delay element 7, based on the counter, a code is received that determines the delay time for the output of the analog and number-pulse signals. From the output of the delay element 7, the connection resolution signal goes to the first information input of the switch 8, the control input of which has a code defining the input address of the information in the computer. Thus, at the moment the signal arrives at the first information input of the switch from the delay element 7, the information determining the value of the analog signal or the state of the number of pulsed signals

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at the time of the survey, can be read from the information output 13 of the switch 8.

Since the frame information is stored in the device memory unchanged until the end of the interpolation interval fj-, i.e. before filling counter 4, the request from the computer can be repeated on an arbitrary or old channel and output 13 of the switch 8 will receive new values of analog or number-pulse signals at the time of polling. At the end of filling counter 4, an information request is generated at its control output 14 for the next frame. At this request, the input is received at input 15 of block 1 of input from an external source of information

I i 7

 1 j of the next frame of information and

recorded in block 2 of the buffer memory. In this case, the coefficients determining the values of the analog signals for the next frame are copied from block 2 of the buffer memory to block 3 of the memory, the value of the interpolation interval is written into the arithmetic unit 5 and the counter 4 times, and the codes determining the number of pulses sensors, iodine to the input of the divider 9. In the future, the device operates in accordance with the above algorithm.

Claims (1)

Invention Formula A device for preprocessing information on the author. St. W 1062684, characterized in that, in order to expand the scope of application due to the formation of the number of pulsed sensors, two counters, a register block and a divider are entered into it, the divider inputs are connected to the first information outputs of the buffer block. the memory, the divider outputs are connected to the information inputs of the register unit, the outputs of which are connected to the inputs of the second counter block, the timestamp outputs of which are connected to the inputs of the first counter block and the control inputs of the register block, the information outputs of the first counter block are connected to the third information input of the switch, the output the overflow of the first block of counters is the output of the Query Device. one Iff / J / 7