RU2075829C1 - Code-to-frequency converter - Google Patents

Abstract

FIELD: automation and computer engineering, in particular, digital control systems. SUBSTANCE: device has pulse generator, flip-flop, two counters, two registers, pulse oscillator, delay gate, two AND gates. Additional AND gates, OR gates and flip-flop are introduced to accomplish goal of invention. Said elements provide two channels which operate in series. Measurement of current period of input frequency is synchronized to in pulse. Output lines of device provide information about last and next to last periods. In addition information about maximal and minimal frequency is stored in memory if necessary. Device may be used in vibration weighing machines. EFFECT: increased field of application due to possibility to store maximal and minimal frequency values. 1 dwg

Description

The invention relates to automation and computer technology and can be used in digital control systems [1]
The aim of the invention is to expand the scope due to the possibility of converting both the measured frequency and its extreme values into code.

 The drawing shows a functional diagram of a frequency to code converter.

 The frequency to code converter contains a pulse shaper 1, elements 2 7 AND, elements 8 11 OR, triggers 12, 13, counters 14, 15, registers 16, 17, pulse generator 18, delay element 19, input 20 bus, inputs 21, 22 control, bus 23 "Reset", bus 24 "Synchronization" and the output bus 25, 26.

 The frequency to code converter operates as follows.

 In the initial state, counters 14, 15, registers 16, 17, trigger 12 are in the zero state, trigger 13 is in the single state, and the outputs of the elements AND 2 7, OR 8 11 are logical zeros.

 The first pulse of the input frequency confirms the zero state of the counter 14 and puts the trigger 12 in a single state, as a result of which the pulses from the generator 18 begin to arrive at the counting input of the counter 14. Note that the filling time of the counter 14 should be longer than the delay time of the delay element 19 and the reset time of the counter 15 taken together, and the delay time of the element 19 should be longer than the response time of the trigger 12, the OR element 8 (9) and the time of recording information in the register 16 (17) taken together, as well as more time switching element in AND 2 (3), OR 8 (9) and the time of recording information in register 16 (17), taken together. In parentheses are the numbers of the elements of the lower arm of the frequency converter.

 Counter 14 starts to fill up. Since the pulses from its output are the reference (coding) for the counter 15, to synchronize the beginning of filling of the counter 15 with the input pulse on the bus 20, it is necessary that the ratio of the pulse repetition period at the input of the counter 14 to the pulse repetition period at its output (namely, this ratio determines the accuracy of synchronization) would be less than the specified accuracy of synchronization. In practice, it is enough that this ratio is equal to 10. Indeed, taking into account that the pulses to the input of the counter 14 come arbitrarily with respect to the bus 20, then after resetting the counter 14 to a pulse from the bus 20, the first pulse at its output will be generated with an accuracy of 1 / 10 periods of coding pulses, i.e. "binding" of coding pulses to a pulse on the bus 20 will be made with an accuracy of 1/10 of the period. If the capacity of the counter 14 is equal to 100, then the accuracy of the "binding" will be equal to 1/100, etc.

 From the output of the counter 14, reference pulses will be supplied to the input of the counter 15 until a second pulse of the measured frequency arrives on bus 20, i.e. until the first period of the measured input frequency ends. The counter 14 will be reset to zero, the trigger 12 will go to the zero state, and logical 1 from its inverse output through the OR element 9 will go to the enable input of the register register 17, rewriting the contents of the counter 15 into it the code of the first period of the input frequency.

 After zeroing, the counter 14 will again accumulate pulses arriving at its counter input. Until the appearance of a coding pulse at its output, a signal is generated at the output of the delay element 19, which will go to the Synchronization bus 24 (signaling from the possibility of removing the code from the information buses 25, 26) and to the input of the “reset” counter 15, translating it into zero state, after which the counter 15 will be ready to record pulses from the output of the counter 14.

 After processing the information from the buses 25, 26, an impulse is received from the external device (not shown in the drawing) to the "Reset" bus 23, which generates a logical 1 at the output of the AND 4 element, which will clear the register 16 through the OR 10 element and prepare it for recording information from the counter 15. Note that the delay time of the element 19, the time of receiving the signal from the external device to the bus 23, the switching time of the elements AND 4 (6), OR 10 (11) and the reset time of the register 16 (17), taken together should be less than the smallest period of the measured frequency.

 When the third pulse arrives at input bus 20, i.e. after the end of the second period of the measured frequency, the counter 14 is reset, and the trigger 12 will go into a single state, while the signal from its output through the element OR 8 will write information (code of the second period) to register 16. Next, the pulse from the output of the delay element 19 will reset the counter 15 and will go to the bus "Synchronization" 24.

 Thus, the code of the first period of the input frequency will be present in the register 17, and the code of the second period in the register 16. Then the process is repeated. The third period code will be present on tires 26, the fourth on tires 25, etc. To highlight the code of the last of the ended periods of the input frequency, you can use the outputs of trigger 12. The presence of a high potential at the direct output corresponds to the code of the last period on the buses 25, and the presence of a unit on the inverse output corresponds to the code of the last period on the buses 26.

 The proposed device can operate in continuous conversion of the input frequency into a code and hold the desired code in one of the registers, which is necessary, for example, when solving the problem of finding extreme numbers. To do this, connect the control bus 22 to the bus "Synchronization" 24, and the control bus 21 to the device for comparing numbers (not shown), which gives a signal to hold the code in the register. Note that this signal must arrive on bus 21 before a reset pulse is generated on bus 23.

 Suppose that a code is searched for the largest period of the input frequency, while the code for the next period is recorded in register 16 as described above. The trigger 12 is in a single state, and a pulse is generated at the output of the delay element 19, which sets the trigger 13 to the zero state.

 If the number recorded in the register 16 is greater than the number in the register 17, then the comparison device generates a pulse to the bus 21, which puts the trigger 13 in a single state. When a reset pulse appears on the bus 23, a logical "1" is formed at the output of the And 6 element, which clears the register 17 through the OR 11 element. The next pulse on the 20 bus will reset the counter 14, will trigger 12 to the zero state. The high potential at the inverse output of trigger 12 will form a logical “1” at the output of OR element 9, which will record the contents of counter 15 into register 17. Then, a signal appears at the output of delay element 19, which will trigger 13 to zero and go to the Sync bus "24.

 If the contents of register 17 is less than the number in register 16, then the comparison device will not give a pulse to bus 21, and the state of trigger 13 will not change. When a reset signal is received on bus 23, the output of element AND 7 will form a logical "1", which will reset register 17 through element OR 11. Upon receipt of the next pulse on input bus 20, trigger 12 will not change its zero state, since its synchronization input logical 0 comes from the output of trigger 13, and the logical "1" is formulated at the output of the And 3 element, which through the OR element 9 will go to the write enable input of register 17 and at the same time rewrite the contents of counter 15 to register 17. Codes of periods of the input frequency will be written go into register 17 until the recorded code is larger than the code in register 17. In this case, the comparison device will translate the trigger 13 into a single state, and when a reset pulse is generated on the bus 23 through the AND 4, OR 10 elements, the register 16. will be reset. when the pulse arrives at input 20, trigger 12 will go into a single state, and the contents of counter 15 will be rewritten into register 16, while in code 17 the code will be stored until more number is entered in register 16 than in register 17.

 Thus, the converter continuously converts the input frequency into code and, if necessary, holds the output information in memory.

Claims (1)

 The frequency converter into a code containing a pulse generator, a delay element, a pulse shaper whose input is an input bus, the output is connected to a trigger input, the direct and inverse outputs of which are connected to the recording inputs of the first and second registers and the first inputs of the first and second elements AND, the second the inputs of which are connected to the reset bus, the outputs are connected to the zero inputs of the second and first registers, respectively, the outputs of which are the output bus, the information inputs of the second register are connected corresponding outputs of the first counter, the input of the delay element is combined with the zero input of the second counter and connected to the output of the pulse shaper, the output with the zero input of the first counter, the counting input of which is connected to the overflow output of the second counter, the counting input of which is connected to the output of the pulse generator , the outputs of the first counter are connected to the corresponding inputs of the first register, characterized in that the third, fourth, fifth and sixth elements And, four elements are introduced into the converter OR and an additional trigger, the zero and one unit inputs are the first and second control inputs, the direct output is connected to the trigger synchronization input and the third inputs of the first and second AND elements, and the inverse output is connected to the first inputs of the third, fourth, fifth and sixth elements And, the outputs of the third and fourth elements AND are connected to the first inputs of the first and second OR elements, respectively, included by the second inputs, respectively, in the communication gap between the output of the first AND element and the input and to zero of the second register, and the output of the second element AND and the installation input to zero of the first register, the outputs of the fifth and sixth elements AND are connected to the first inputs of the third and fourth elements OR connected by the second inputs, respectively, to the communication gap of the inverse output of the trigger with the recording input of the second register and a direct trigger output with the first register entry input, the second inputs of the third and fourth AND elements are combined and are the "Reset" bus, and the third inputs are connected respectively to the inverse and direct outputs of the trigger Pa, the second inputs of the fifth and sixth AND elements are combined and connected to the output of the pulse shaper, and the third inputs are connected respectively to the inverse and direct outputs of the trigger, while the output of the delay element is the "Synchronization" bus.