SU1539758A1 - Programmable shaper of periodic function - Google Patents

Abstract

A programmable periodic function shaper relates to digital computing and can be used in hybrid computing complexes and automation devices with a programmable specification of functions of a complex form. The purpose of the invention is to reduce equipment. The programmable driver contains an address memory block, two address registers, an address selector, a synchronization block, a buffer register, a period counter, a digital-to-analog converter, an output register, an And element, a single vibrator, and a group of N function value memory blocks. The goal is achieved due to the fact that the driver contains a group of N memory blocks of function values. 2 Il.

Description

The invention relates to digital computing and can be used in hybrid computing complexes, automation devices and computing technology with a programmable assignment of functions of a complex form.

The purpose of the invention is to reduce equipment

The essence of the invention is that each code of the output value of the function Y is represented as a composition

Y (t ,, t2, ..., tp),

where t- (i 1, p) are parts of the function value codes stored in separate memory blocks

Figure 1 shows the functional diagram of the programmable generator of a periodic function; Fig 2

functional block diagram synchronization.

A programmable periodic function generator (FIG.) Contains an address memory block 1, a group of blocks 201 —23p of a function value memory (where n is the number of code parts of the function's output value code), a synchronization block 3, a buffer register 4, the first address register 5, the second address register 6, output register 7, 8 period counter, digital-to-analog converter 9, address selector 10, AND 11 element, one-shot 12, first information input 13, start input 14, second information input 15 and driver 16 output

The synchronization unit 3 (FIG. 2) contains a trigger 17, a clock pulse generator 18 and a ring register 19o.

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SL

with

SP

00

The programmable periodic function generator works as follows.

In the initial state, the memory elements of the former are in the zero state. From the control output of the output register 7, the signal log.11, which identifies the sign of the end of the period, goes to the control input of the address selector 10 and allows the information from the output of the buffer register 4 to pass through it

Information about the code of the program for forming the function and the number of periods for its working out is received respectively from inputs 13 and 15 and is entered into the buffer register 4 and the counter for 8 periods. At the same time as these codes are fed, input 14 of the driver receives the control signal at the beginning of work. According to this signal, trigger trigger 17 () of synchronization unit 3 goes into one state and enables the generation of clock pulses at the output of generator 18. These pulses go to the clock input of the ring register 19, at the outputs of which pulses are sequentially output to synchronize the operation of the driver.

On the first clock pulse from the output of the synchronization unit 3, which arrives at the synchronizing input of the register 5 of the address, the information through the address selector 10 is entered into this register. The information entered into the address register 5 represents the starting address of the function generation program. On the second clock pulse, information is sampled by the address entered in register 5 from block 1 "

The programmable converter implements a two-level approach to forming the output function codes. The first level is the address level in which the address codes of the reproduced functions are stored in block 10. The values of the functions themselves are stored in blocks 201 -, 2.p memory and form the operational level. At the same time, the address level controls the operational level. Such an approach to the formation of function codes increases flexibility and reduces the required amount of memory based on the elimination of repetitive function codes.

On the next clock pulse from the output of the synchronization side 3, information about the address codes from the outputs of block 1 is entered into the address register L of the address.

0

five.

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0

five

0

five

0

five

The next clock pulse is used to call blocks 2-2-2 memory to read parts of the code of the output function. The read information (the code of the function being formed) on the next clock pulse is entered into the output register 7, from the output of which it enters the input of the digital-analogue converter 9 and after conversion to analogue, arrives at the output 16 of the programmable driver.

After writing the function code to the register 7, a log appears on its control output. This signal arrives at the control input of the address selector 10 and thereby permits the passage of the code of the next address from the output of block 1.

The first clock pulse from the output of the synchronization block 3 of the next pulse sequence of information from the first output of block 1 through the address selector 10 is entered into the address register 5 and the function code is generated in a manner similar to that considered.

Simultaneously with the formation of the last code of the function of the period in question, a control sign of the end of the period is formed on the control output of the register 7. This signal arrives at the control input of the address selector 10 and permits the rewriting of information from the buffer register 4 to the address register 5. In addition, the appearance of the mark-sign of the end of the period of the function being formed reduces the contents of the counter of 8 periods by one, which characterizes the end of the formation of the function in one period. Next, the driver functions in the same way until the counter of 8 periods is reset. The zeroing of the latter means the end of the formation of a given number of periods of the function being formed.

When the counter is cleared to 8 periods, the output of the element 11 is formed. A signal is generated at the output of the one-oscillator 12, which is fed to the input of the synchronization unit 3 (FIG. 2) and the start trigger 17 is zeroed. At this programmable driver completes its work.

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Claims (1)

Programmable <periodic function, address memory, two address registers, address selector, synchronization block, buffer register, period counter, output register, one-shot, AND element, and the first information input of the driver is connected to the information input of the buffer recorder and the address block is connected to i- mu (ί = 1, η) to the information input of the second address register, the fourth output of the synchronization unit is connected to the synchronizing input of the output register, the discharge output of the sign is connected to the selector period of the address of the period counter, the information input of which is connected to the second information input of the shaper, the end of the period of the co-control input and the subtracting input of pa, the synchronization input of which is connected to the recording permission input of the shaper, the output of the buffer register is connected to the first information input of the address selector, the output of which is connected to the information the input of the first register'address, the synchronizing input of which is connected to the boot enable input of which is connected to the synchronization input; periods, the inverse outputs of the period counter are connected to the inputs of the And element, the output of which through a single-shot is connected to the stop input of the synchronization unit, the output of the output register is the fork output to the first output of the synchronization unit, the second output of the synchronization unit is connected to the control input of the address memory unit, information input co-driver, characterized in that, in order to reduce equipment, the shaper contains a group of η blocks of function values that are connected to the output of the first pe25 and the outputs fields of the second address register, the transition output of the address memory block is connected to the second information input of the address selector, the driver start input is connected to the first input of the synchronization block, the third output of which is connected to the synchronizing input of the second address register, i-th output of the group of outputs (1 = 1, o) the memory block ra addresses are connected to the corresponding from the first to the i-th information inputs of the group of blocks of memory values of the function, the outputs of which are connected to 30 corresponding information inputs of the output register, The Fifth output synchronization unit connected to the memory block group synchronization inputs of the function.,