SU1246374A2 - Sine-cosine signal-to-digital converter - Google Patents

Abstract

The invention relates to automation and computing and can be used to connect analog information sources with a digital computing device. In order to increase the accuracy of the converter by correcting the output value, 1pF Cosf (L

Description

By the code of the error known in advance, sine-cosine signals are converted in block 1 into a system of multiphase signals. Depending on the ratio of the amplitude of the input signals of the converter, a single j signal is formed at one of the codes of the decoder 2. The value of the previous signal is stored in register 3. In blocks 4 and 5 of the elements AND, the code values of the current signal are compared with the previous one. When changing to one side of the current code as compared to the previous one, pulses are generated at the output of the element OR 6, the code of the reversible counter 8 changes by 1 V

The invention relates to auto amateurs and computing, can be used to connect analog information sources with a digital computing device, and is an improvement to the invention by author. No. 1094043.

The purpose of the invention is to increase the accuracy of the converter by correcting the value of the output code according to the most advanced error value.

FIG. 1 shows a converter block diagram; in fig. 2 is a block diagram of the correction unit.

The converter contains a sine-cosine transformation block 1; signals into multiphase sig.pa, the outputs of which through the decoder 2 are connected to the information inputs of register 3 and to one groups of inputs of the first 4 and second 5 blocks of elements AND, D1eg groups of inputs of which are connected to the outputs of the bits of the register 3, and the outputs of the first 4 and second 5 blocks of elements AND are connected respectively to the inputs of the first 6 and second 7 elements OR, the reversible counter B, the driver 9 pulses, the inputs of which are connected to the outputs of the elements OR-6 and 7, and the output connected to the synchronizing input of the register 3. Outputs cops OR 6 and 7 are connected to the first and second input46374

one side, and the contents of the decoder 2 is rewritten into register 3 by the output pulse of the former 9. When 1 is changed to the other side of the current code, pulses are generated. at the output of the element OR 7, and the code of the reversible counter 8 is changed to 1 in the other direction, and the contents of the decoder 2 is rewritten in the register 3. In the correction block 10 is stored the correction code, which, depending on the output code of the reversible counter 8 and the direction of its change is entered through the elements OR 1 1, 1, and 12 at the inputs of the addition or subtraction of the reversible counter 8. 1.c. ff, 2 ill.

I will give a correction block 10, a group of inlets. : the ports of which are connected to the outputs of the bits of the reversible counter 8.- The output of the element OR 6 and the first output 5 of the block 10 through the element OR 11 are connected to the input of the reversible counter 8, and the output of the element RSII 7. and the second output of the block 10 through the element OR 12 - to the input of the subtraction of the reverse version of the counter 8.

Correction unit 10 contains drivers 13 and 14 pulses, memory block 15, first 16, second 17, third 18 and fourth 19 elements And, first

5 20 and second 21 elements OR. The inputs of the driver 13 and 14 of the pulses are the first and second inputs of the correction block 10, and the inputs of the memory block 15 are a group of inputs of the block 10

0 correction. The first output of the memory block 15 is connected to the same inputs of the elements And i6 and 17, the second output of the block 15 to the same inputs of the elements AND 18 and 19. The output of the former 13 sub5 is connected to the other inputs of the elements

And 16 and 19, and the output of the shaper 14- to the other inputs of the elements And 17 and 18. The outputs of the elements And 16 and t8 are connected to the inputs of the element OR 20, the output.

0 which is the first output of the correction unit 10, and the outputs of the AND elements 17 and 19 are connected to the inputs of the OR element 21, which is the second output of the correction unit 10.

The converter works as follows.

In block 1, the input sine-cosine signals are converted into square multi-phase signals, the number s of which is determined by the received converter discreteness. In decoder 2, multi-phase signals are converted into sequences of non-overlapping pulses, which are

arrive at the inputs of blocks 4 and 5 of the elements And and the information inputs of the register 3.

At any time, the signal at the output of the decoder 2 is 15 of itself 1 at one of the outputs and O at all other outputs. According to the signal from the former 9, the state of the decoder 2 is stored in register 3. The codes of the decoder 2 and register 20

3 are compared in blocks 4 and 5. With the equality of the output codes of the decoder 2 and register 3, all the outputs of the blocks

4 and 5 are in the zero state. When the input value of 25 is changed to one side, the output code of the decoder 2 successively takes the values, for example, 1000, 0100, 0010

etc,

With each change of the output code of the decoder 2, a match occurs on one of the elements AND block 4 of the unit of the code of the previous value from register 3 with the unit of the code of the current value of the decoder. 2. Single. The signal from the output of block 4 through the elements of RSHI 6 and 11 passes through the input of the addition of the reversible counter 8 and through the driver 9, which is the OR element and the delay element, arrives at the control input of register 3. At a signal from the driver 9 V Register 3 overwrites the output code of the decoder 2, after which the output codes of the decoder 2 and register 3, with become equal. The outputs of block 4 return to the zero state until the next change in the input value in the same direction.

When the input value changes to 50, the other side of the output code of the decoder 2 takes the values, for example, 1000, 0001, 0010,0100, etc. Each time the output code of the decoder 2 changes, a match 55 occurs on one of the elements AND block 5 of the unit of the previous value code from register 3 with the unit of the current value

35

s Q

15 20

25

zo with

0 5

five

the values from the decoder 2. A single signal from the output of block 5 through the elements OR 7 and 12 passes to the input of the subtraction of the reversible counter 8 and through the driver 9 to the control input of the register 3 to overwrite the output code of the decoder 2. The outputs 5 return to zero state until the next change the input value. The output code of the converter is generated in a reversible counter 8.

The output code of the counter 8 to form c. The specified points of the single correction signals are fed to the first and first inputs of the correction block 10. Unit- Signals from blocks 4 and 5 through the elements OR 6 and 7, respectively, arrive at the first and second inputs of correction block 10, from which in the intervals between unit signals from blocks 4 and 5, single correction signals are received through elements OR 11 and 12 to the corresponding reversing inputs counter 8.

Each cell of block 15 contains the correction code 10, or 01, or 00. This means that when the code of the reversible counter takes the value corresponding to the address of the cell in which it is written, for example, code 10, then at this value of the input quantity and its growth into the counter 8 it is necessary to make a +1 correction, when the input value decreases. We need to make a correction of -1. If the code in the cell is 01, then as the input value increases, a correction of -1 is needed in the counter, and +1 when decreasing, Code 00 means no correction at this point.

The address buses of the block 15 may not be fed to the lower bits of the reversible counter 8. The number of these bits is determined by the minimum length of the section where a single correction value is required.

Using elements AND 16-19, the correction code recorded in the cell of block 15 is transmitted to the summing or subtracting input of the reversible counter 8, depending on the direction; change the input value.

The shapers of 13 and 14 pulses produce, after each of the pulses received from the elements OR 6 and 7, correction pulses.

In the out-of-touch system, these pulses are formed by cutting the pulses from elements 6 and 7 with some

delayed. In a system with two sequences of clock pulses shifted 180 one relative to another, the pulses from elements 6 and 7 are generated along the first, and from the formers 13 and 14 through the second sequence of pulses so that the correction pulses go to counter 8 between main impulses.

In converters in which the reference can be set arbitrarily, the correction unit must include an additional counter, the outputs of which are fed to

the address inputs of the memory unit 15, in which, at the start of operation, the true (absolute) value of the input quantity should be entered.

If the address inputs of the counter 8 give a signal about the direction of change of the input value, then, with the same value of the input value, it can be given a different correction value depending on the direction. changes in the input value, thus compensating for hysteresis. Thus, comparing before the beginning

operation of the code value converter; of one value with its true value over the entire range of variation of the input value, it is possible to add unit corrections to the corresponding cells of the memory block, which increases the accuracy of the converter.

Claims (1)

1. Converter sine-cosine signals in the code azt.sv. No. 1094043, distinguishing with. In order to improve the accuracy of the converter, a correction block is introduced into it, the third and fourth elements ten 37 A6 You are OR, the first and second elements OR are connected to the same inputs of the third and fourth PW elements and to the first and second inputs of the correction unit, the group of inputs of which is connected to the outputs of the bits of the reversible counter, and the first and second outputs of the correction unit are connected to other inputs the third and fourth elements OR, the outputs of which are connected to the inputs of the addition and subtraction of a reversible counter. 2, the converter according to claim 1, in that the correction unit comprises the first and second pulse formers, the memory block, the first, second, third and fourth And elements and the first and second OR elements, the inputs of the first and second formers the pulses are the first and second inputs of the correction unit, and the inputs of the memory unit are a group of inputs of the correction unit, the first output of the memory unit is connected to one input of the first and second And elements, the second output of the memory unit is connected to one input of the third and fourth elements And, runner. the first pulse shaper is connected to the other inputs of the first and fourth And elements, the output of the second pulse shaper is connected to the other inputs of the second and third And elements, the outputs of the first and third And elements are connected to the inputs of the first element. This OR, the output of which is the first output of the correction unit, and the outputs of the second and fourth AND elements, is connected to the inputs of the second OR element, the code of which is the second output of the correction unit. V1MIPI 4022/56 Circulation 816 Subscription Random polygons pr-tie, Uzhgorod, ul, Proektna, 4 Subscription