SU1011623A1 - Data recorder - Google Patents

Abstract

A DEVICE FOR INFORMATION RESISTANCE, containing scanning blocks connected by corresponding shaper and signal transmitters connected to the corresponding synchronization blocks, the elements AND whose inputs are connected to the register and the first counter and the output; : are connected to the inputs of the elements OR, whose outputs are connected to the inputs of the corresponding synchronization blocks, a voltage to pulse frequency converter connected to a digital: analogue converter and to the first counter, so that In order to increase the speed of the device, it contains serially connected frequency dividers connected to the output of a voltage-frequency converter, pulse switch, and a reversible counter whose outputs (O are connected to the inputs of the switch AND alogovogo converter.;

Description

The invention relates to automation and computer technology, in particular to devices for recording information, and can be used in the output of graphic information from a computer. A device for recording information is known, containing an execution unit whose drive is connected to the control unit, a logic unit connected to the control unit and to the counter, the input of which through the element I is connected to the pulse generator, the digital-to-analog converter and the input register of the GP. The disadvantage of this device is its low speed,. The closest to the invention is a device containing scanning blocks, the inputs of which are connected to signal conditioners, and the outputs are connected to feedback signal sensors, the outputs of which are connected to the inputs of the corresponding synchronization blocks, OR elements, whose inputs are connected to AND elements, connected to the register and to the counter, digital-to-analog converter and logic block C2J. A disadvantage of the known device is the low dynamic accuracy limiting the speed of the device. The purpose of the present invention is to reduce dynamic errors and increase the speed of the device. The goal is achieved by the fact that, in a known device, containing scanning blocks connected to the corresponding signal conditioners and sensors connected to the corresponding synchronization blocks, AND elements whose inputs are connected to the register and the first counter, and the outputs are connected to the inputs of the OR terminals, the outputs of which are connected to the inputs of the corresponding synchronization blocks, the voltage to pulse frequency converter connected to the digital-analog converter and to the first counter are entered after Successively connected frequency divider connected to the output of a voltage to pulse frequency converter, a switch and a reversible counter, the outputs of which are connected to the inputs of a switch and a digital-to-analog converter. The drawing shows a block diagram of the device. The device includes the first counter 1, elements AND 2, register 3, elements 4 OR, synchronization blocks 5, signal formers 6, scan blocks 7, signals sensors 8, voltage to pulse frequency converter 9, digits — analog converter 10, second counter 11, switch 12, frequency divider 13. The device works as follows. Information About the projections of the reproducible direct is in the register 3 of the current coordinates, each of the bits of which is connected to the elements 2 I. The pulses from the voltage converter 9 to the pulse frequency are fed to the input of the counter 1, where the frequency of their division is divided in accordance with the bit dami counter. 1F pulses taken from bits of counter 1 are fed to input of elements 2 AND, where the contents of register 3 and bits of counter 1 are compared, resulting in the number of pulses equal to To the code of the corresponding projection of the direct, located in the register 3, these pulses are supplied to the synchronization units 5, where they are synchronized and separated from the pulses of the sensors 8 of the feedback signals. ; b in accordance with the arrival of the reference and feedback pulses, the formers 6 generate control signals for the scanning blocks 7, the state of which is fixed by the sensors. tracking system f formed by block 5 by shaper 6 of signals, block 7 and sensor 8 of feedback signals. When applying a sequence of high-frequency pulses due to the inertia of block 7, the dynamic error may exceed up to a NULL. This limits the speed limit of the driver and the speed of the device as a whole. To avoid this limitation is achieved in that in the proposed device the frequency of the pulses at the input of counter 1 increases smoothly according to the exponential law. This reduces the dynamic error and achieves a large final speed. The experimental increment law is due to the fact that the initial frequency pulses are fed not only to the input of counter 1, but also through the frequency divider 13 and switch 12 to the summing input of the reversible counter 1 1. The latter causes an increase in the code in the counter 11, which. leads to an increase in voltage at the output of the digital-to-analog transforming the bodies 10 and; respectively, the frequency; pulses on the inverter I 9. The frequency rise zone is described; The NOMA law is defined by the resolution of the Gcifro analogue; the transducer is | l 10.

As soon as the frequency of the pulses at the output of converter 9 reaches the required value, the digital-to-analog converter 10 becomes saturated, which leads to the appearance of a constant voltage at its output and the establishment of a constant frequency

impulses at the output of the converter 9.

The filling of the counter 11 indicates that the formation of half of the required number of pulses is completed, that is, half of the straight is reproduced. On this signal, the switch 12 switches the pulses from the frequency divider 13 to the subtractive input of the counter 11. The code value in it decreases. When entering the deceleration zone, the digital-to-analog converter 10 goes out of saturation and the pulse frequency from the converter output exponentially decreases. 9. This avoids the dynamic, error in the deceleration section. Frequency divider 13 is necessary to set the frequency of the growth rate (exponential law coefficient). The higher the frequency division ratio, the more smoothly the frequency increases. The direct playback ends when the code I is zero in counter 11.

The introduction of new components and elements, as well as new constructive links, allows to significantly increase the speed of the device.

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Claims (1)

DEVICE FOR INFORMATION REGISTRATION, containing scan blocks connected to the corresponding shapers and. • sensors of signals connected to the corresponding synchronization units, AND elements, the inputs of which are connected to the register and the first counter, and the outputs. connected to the inputs of the OR elements, the outputs of which are connected to the inputs of the corresponding synchronization units, a voltage to pulse frequency converter connected to a digital: analog converter and to the first counter, characterized in that, in order to increase the speed of the device, it contains a frequency divider connected in series connected to the output of the voltage converter to ν pulse frequency, the switch and a reversible counter, the outputs of which are connected to the inputs of the switch AND digital-to-analog conversion the caller. . ^ SU „, 1011623