SU1151994A1 - Device for determining ratio of two voltages - Google Patents

Abstract

.one. A DEVICE FOR DETERMINING A RELATION OF TWO VOLTAGES, comprising a code-controlled resistor, a comparator unit, a digital-to-analog converter and a switch connected by a control input to the first output of the synchronization unit, which is additionally introduced in order to improve the speed and accuracy of determining the ratio of the synchronization unit by means of a synchronizer unit, it is equipped with a driver, and the drivers in this device have to implement a number of drivers into the control unit, which is equipped with a control signal, which, in particular, has to be equipped with a number of drivers in the control unit, which is equipped with a trigger input and a switch that has been connected to the control unit. counter, elements AND and NOT, two buffer registers and a generator of counts of pulses, connected by an output with the first inputs of the first and second elements AND, connected by outputs to the counters of the first and second reversible counters, respectively, the second input of the first element I is connected to the second output of the synchronization unit and the input of the initial setup of the first buffer register connected by the write enable input to the third output of the synchronization unit, the second input of the second And element and the first input of the third element And, information inputs to the outputs of the bits of the second reversible counter, and outputs to the inputs of a digital-to-analog converter, connected to the output of the first input of the block A comparison, connected by the second input to the output of the coded resistor, the first output to the control input of the reverse of the first reversible counter and the input of the element NOT, and the second output of the input to prohibit the counting of the first and second reversible counters and to the second input of the third element And connected by the output to the enable input (L of the second buffer register record, the bit outputs of which are the device outputs, and the information inputs are connected to the bits of the second reversible counter, the connected input The control of the reverse with the output of the element is NOT, and the SP outputs of the bits of the nerve reversible counter are connected to the control terminal from the inputs of the code-controlled resistor connected by the signal input to the output of the switch, the first and second signal inputs of which are the device inputs. 2. The device according to claim 1, wherein the synchronization unit contains a trigger, an AND element and a pulse generator, the output of which is the first output of the synchronization unit and connected to the counting trigger input and to the first inputs of the first and second AND elements connected by the second inputs

Description

to the direct and inverse outputs of the trigger, respectively, and the outputs to the second and third outputs of the synchronization unit.

3. The device according to claim 1, wherein the comparison unit contains comparators, elements AND and NOT, and an adjustable voltage resistance divider connected by the first input to the comparison unit and the first input of the first comparator, the second the output to the zero potential of the comparison unit, and the output of the moving contact to the first input of the second comparator connected by the second input to the second input of the comparison unit and the second input of the first comparator, and the output to the input of the element NOT and to the first input of the first element I, by connected to the first output of the comparison unit, and the second input to the output of the first comparator and the first input of the second element AND, the second input and output of which are connected respectively to the output of the element NOT and the second output of the comparison unit.

The invention relates to the field of automation and computer technology and can be used in hybrid computing devices and systems, in particular, when performing the conversion of the ratio of two voltages into a digital code. An analog-to-digital dividing device is known comprising a code-voltage converter, a counter, a comparison unit, an AND element, and a TJ clock pulse generator. It is also known that a separating device containing a synchronization unit, keys, a clock pulse generator, an AND element, a reversing counter, and a digital-to-analog converter t2 1. The disadvantages of these devices are reduced speed and accuracy. Closest to the invention is a device for determining the ratio of two voltages, containing two coding transistors, a comparison unit, a digital analog transducer, a reference voltage source, a program block, trigger groups and two commutators, the first of which is connected by signal inputs to the outputs the first codecontrol of the resistor and the digital-to-analog converter that controls the input to the first output of the synchronization block, and the output to the first input of the comparator connected by the second input to the output meters of the second switch, connected to the signal inputs to the outputs of the second code-controlled resistor and the reference voltage source, the first and second code-controlling resistors are connected by signal inputs to the device inputs, and the control inputs g to the output switches of the group of digital inputs connected to the digital inputs the converter, and the outputs of the software block, which is connected by a signal input to the output of the comparison block C3. The disadvantages of the known device are reduced speed Wie and accuracy because of increased costs involved in the processing of the first and second cycles of converting m errors caused you nonidentity) tolneni kodoupravl proxy resistors. The aim of the invention is to increase the speed and accuracy of determining the ratio of the two voltages. The goal is achieved by the fact that the device for determining the ratio of two voltages, the contents (its code-controlled resistor, the comparison unit, the digital-to-analog converter and the switch, connecting the control input to the first output of the synchronization unit, additionally introduced two reversible counters, elm {Ggy) AND and NOT, dvd buffer register and a generator of counting pulses connected to the output of the first inputs of the first and second elements And connected to the outputs of the counting inputs of the first and second reversible counters respectively However, the second input of the first element AND is connected to the second output of the synchronization unit and the input of the initial setup of the first buffer register connected by the write enable input to the third output of the synchronization unit, the second input of the second element I and the first input of the third element AND, information Q inputs to the bits of the second reversible counter, and outputs to the inputs of a digital analog converter connected by an output to the first input of the comparator unit connected by the second input to the code control output first resistor to the control input of the reverse of the first reversible counter and the input of the element NOT, and the second output to the inhibit inputs of the first and second reversible counters to the second input of the third element I connected to the input of the recording resolution of the second buffer register the ports of which are inputs of the device, and information inputs are connected to the outputs of the bits of the second reversible counter connected by the control input of the reverse with the output of the element H and the outputs of the bits of the first p versivnogo connected to the counter. control inputs of a code-controlled resistor connected by a signal input to a switch output, the first and second signal inputs of which are input devices. In addition, the synchronization unit contains a trigger, an element And an impulseV generator, the output of which is with the first output of the synchronization unit and connected to the counting input of the trigger and with the first inputs of the first and second And elements connected by the second inputs to the direct and inverse trigger outputs, respectively, and outputs to the second and third outputs of the synchronization unit. The comparison unit contains comparators, AND and NOT elements, and an adjustable resistive voltage divider connected by the first output to the first input of the comparison unit and the first input of the first comparator, the second output to the zero potential bus of the comparison unit, and the output of the movable contact to the first input of the second comparator connected by the second input to the second input of the comparison unit and the second input of the first comparator, and the output to the input of the element NOT to the first the input of the first element I connected by the output to the first output of the comparison unit, and the second input to the output of the first comparator and to the first input of the second element I, the second input and output of which are connected respectively to the code element HE and that the second output of the comparison unit. Fig. 1 shows a block diagram of a device for determining the ratio of two voltages; figure 2 - diagram of the synchronization unit; Figure 3 is the same as the comparison block. The dp device for determining the ratio of two voltages (Fig. 1) contains the switch 1, the first 2 and the second 3 inputs of the device, the synchronization unit 4, the code control resistor 5, the comparison unit 6, the digital-analog converter 7, the first reversible counter 8, the first buffer register 9, the second reversible counter 10, the second buffer register 11, the generator 12 counting pulses, the first and second elements And 13 and 14, the element 15 and the third element And 16. The synchronization unit 4 (figure 2) contains the generator 17 pulses, trigger 18 , the first and second elements And 19 and 20, and with the first About on the third exits 2123. Comparison unit 6 (FIG. 3) contains the first 24 and second 25 comparators, an adjustable resistive voltage divider 26, a NOT element 27, the first and second elements 28 and 29, the first and second inputs 30 and 31 of the comparison block and the first and second outputs 32 and 33 of the comparison unit. The device works as follows. The synchronization unit 4 performs the shaping at the first output of a 14eander type pulse train with a period T, performing sequential switching of switch 1, and forming on the second and third outputs two pulse sequences with a period of 2T each shifted relative to each other by time T. Conversion of input voltages zheniy and and 7/0; V 70) entering the inputs 2 and 3 of the device, in the digital equivalent of their ratio, are carried out in two cycles. In the first cycle for the pulse time from the first output of unit 4, switch 1 connects the voltage divider} to the input of the co-controlled resistor 5. Simultaneously With this signal, AND 13 is unlocked from the second output of block 4, and in register 9 the initial code value is set to be equivalent to one. By changing the state of the reversible counter 8, the value of the conversion coefficient K of the resistor 5 is established, which satisfies the relation U, Kj-K, Nv ,,, t, C1) where D is the difference of the voltages supplied to the inputs of the comparison unit; K-, - constant conversion factor of the digital-to-analog converter 7; - threshold of operation of unit 6 of the comparison unit (it can be regulated by changing the position of the moving contact of the divider 26). The logic of operation of the comparison unit 6 is as follows. In the case of D7, the signals at the first and second outputs 32 and 33 of block 6 take on the values of logical zero. In the case, the signal at the first output 33 of the comparator takes the value of the logical unit, and at the second code 33, the logical zero. If, however, the voltage at the second output of the comparison unit takes the value of the logical one regardless of the value of the signal at the first output. the generator pulses 12 through the element And 13 arrive at the counter input of the counter 8, increasing its output code with & or decreasing the output code of the counter with D7, which respectively leads to an increase or decrease in the current coefficient value transmitting the resistor 5. The change of this coefficient continues until the occurrence of a logical unit on the second high, during block 33, i.e. until inequality (1) is satisfied. The signal from the second output of the comparison unit 6 is fed to the input of the prohibition of the counting of the counter 8, fixing its contents ... After the pulse at the second output of the synchronization unit 4, the element And 13 is locked, ensuring that the received transmission coefficient is saved for the second cycle time. In the second cycle of operation, switch 1 connects to the input of resistor 5 the voltage of the dividend and. Pulse from the third output of the synchronization unit 4 is unlocked element I 14, permission to transfer the output code of the counter 10 to this register is fed to register 9. In this cycle, the code is continuously transferred to the register 9 and the digital-to-analog converter in the reverse text counter 10. The 7 is converted to the voltage U-K, which is fed to the first input of the comparison unit 6, at the second input of which at this time the voltage from the output of the resistor 5 is equal to and, "Since the control input of the reverse of the counter 10 is connected to the first output of the unit 6 comparisons through the cut element NOT 15, then with UJ-UT.- the output code of the counter 10 decreases, and when the increase of this code until the moment of satisfaction of the ratio lUj-U (fixed by the appearance of a single signal at the second output of block 4). In this case, the output code of the counter 10 is This makes the condition UT Kjg and EiN.N 10 10.1 Uj, K, U From expression (3) it follows that when the counter N is generated in the second cycle, the code N expresses the sought value of the ratio of input voltages with the multiplicative error, At the end of the code generation at the emitter 10, an element 16 is unlocked with a second output signal, the 16th element is opened (the first input of which is supplied with a single signal from the third output of the block and the counter code 10 is rewritten to register 11, where this code is stored until the end of the next cycle operation. Thus, when the input voltages of the dividend and divider change in the proposed device, in each work cycle, only the transfer coefficient of the resistor 5 (at the first cycle) and the counter code 10 are adjusted, which ensures the tracking mode of the proposed device and a higher speed than famous. At the same time, a single-channel structure that transforms both voltages in the same code-controlled resistor 5 with the same transform coefficient provides a significant reduction in the error in the formation of the digital voltage ratio code.

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Claims (3)

1. A DEVICE FOR DETERMINING THE RELATIONSHIP OF TWO VOLTAGES, containing a code-controlled resistor, a comparison unit, a digital-to-analog converter, and a switch connected by a control input to the first output of the synchronization unit, in order to improve performance and the accuracy of determining the relationship, it additionally introduced two reversible counters, AI elements NOT, two buffer registers and a counting pulse generator connected by the output to the first inputs of the first and second AND elements connected by outputs to the input inputs of the first and second reversible counters, respectively, with the second input of the first element And connected to the second output of the synchronization unit and the input of the initial setup of the first buffer register connected to the recording enable input to the third output of the synchronization unit, the second input of the second element And and the first input of the third element And, information inputs to the outputs of the bits of the second reversible counter, and outputs to the inputs of the digital-to-analog converter, connected by the output to the first input of the comp connected by the second input to the output of the code-controlled resistor, the first output - to the control input of the reverse of the first reversible counter and the input of the element NOT, and the second output - to the inputs of the counter prohibition of the first and second reversible counters and to the second input of the third element And, connected by the output to the input write permissions of the second buffer register, the outputs of the discharges of which are the outputs of the device, and the information inputs are connected to the outputs of the discharges of the second reversible counter connected by the control input Som yield NOT element, wherein the outputs of bits pervbgo down counter connected to the control inputs kodouprallyaemogo resistor connected to the signal input of output switch, the first and second signal inputs of which are the inputs. 2. The device according to claim 1, wherein the synchronization unit contains a trigger, an element And a pulse generator, the output of which is the first output of the synchronization unit and is connected to the counting input of the trigger and to the first inputs of the first and second elements And, connected by the second inputs to the direct and inverse outputs of the trigger, respectively, and the outputs to the second and third outputs of the synchronization block. 3. The device according to claim 1, wherein the comparison unit contains comparators, AI elements NOT, and an adjustable resistive voltage divider connected by a first output to the first input of the comparison unit and the first input of the first comparator, and the second output to the bus zero potential of the comparison unit, and the output of the movable contact ta - to the first input of the second comparator, connected by the second input to the second input of the comparison unit and the second input of the first comparator, and the output - with the input of the element NOT and with the first input of the first element And, connect chennogo output to the first output of the comparator, a second input to the output of the first comparator and to the first input of the second AND gate, a second input and whose output is connected respectively to the output of NOT circuit and the second output of the comparator. ♦