SU620018A1 - Analogue-to-digital conversion device - Google Patents

Description

(54) DEVICE ANALOG-DIGITAL TRANSFORMATION

one

The invention relates to the technique of analog-to-digital conversion and can be used when transmitting analog signals over discrete communication channels.

A coding adaptation adapter is known in which the number of codeword bits varies according to the measured akin value of the code signal ij.

A disadvantage of such a device is the inability to monitor rapidly changing, for example exponentially, input signals, as well as redundancy in coding signals, due to the difference in the current value of the signal from the measured average level.

The closest in technical essence to the claimed invention is an analog-to-digital converter comprising a comparison unit, a logic device, a cocTosnaee of AND elements and a switch, a memory unit, a diffraction-analog converter and a pulse generator 2.

The lack of tax on the device is a lack of redundancy in the discrete representation of small input signals, which is expressed in the fact that in this case the higher bits are zero and transmitting them over the communication channel is impractical.

The aim of the invention is to eliminate redundancy during coding.

input signals.

This goal is achieved by the fact that the inventive device comprising a comparison unit, the first input of which is connected to the input signal bus,

the second input is with the output of a digital-to-analog converter, and the output is connected to the first inputs of each of the W, AND elements, the second inputs of which are connected respectively to the outputs with

2 - (m + l) of the switch, the outputs of the latter are connected respectively to the first inputs of each of the -HU memory elements, their second inputs are connected respectively to the W outputs of the switch, the outputs of which are connected respectively to the HS inputs of the digital-to-analog converter, the control inputs of the switch They are connected to the starting pulse bus and the clock pulse generator output, a reverse meter counter and two logic elements, the first, are added. | T1 inputs of these elements are connected to the memory outputs of the memory elements, the second, 1g inputs of which are connected to the corresponding inputs of the switch and m outputs of the reverse counter, the subtractive and summing inputs of which are connected, respectively, with the outputs of the first and second logic elements. The drawing shows the structural electrical circuit of the proposed device of a digital transform1 "l. The device contains a flea 1 of comparison whose first input is connected to the bus 2 of the input signal, the second input about the output of the digital-to-analog converter 3, the output of the cod to the first inputs of each of the elements 4, the second inputs of which are connected with 1 with the outputs 2 - (-Tn -f 1} of the switch 5, and the outputs of the B 4 and 4 are connected to the first inputs of each of the memory elements 6, their second inputs are connected respectively to the W outputs of the switch 5, and the outputs of the elements on the 6 and 6 are corresponding to the digital inputs of the analog converter 3 and with the first and inputs of logic elements 7 and 8, the second; HU inputs of the latter are connected respectively with the inputs of the switch 5 and with the outputs of the reversible counter 9, and the outputs of the logic elements 7 and 8 are connected respectively with the subtracting and summing inputs of the reversible counter 9, controlling The inputs of the switch 5 are connected to the bus 1O of the starting impulses and the generator output 11. Clock pulses. The device operates as follows. The starting impulse arriving at the control input of the switch 5 rewrites the contents of the reversing counter 9, KOTOpiDe and in the initial state is zero, in the counting switch, T-pulses arriving at the control input of the switch 5, alternate from the generator output 11 clock pulses on one of the (ti-1) outputs of switch 5, starting with (1 +1), where i is the contents of the reversing counter 5, i.e. the first pulse appears at the (i +1) -th output, the second pulse at the (i + 2) -th, etc. Using these pulses, the input analogue value is transformed using a serial encoding method to binary (JT1 - i) the bit number is due to the use of the elements AND 4, the memory elements 6, the analogue converter 3, and the comparison unit 1. At the end of the conversion cycle, the analysis of the received binary chip begins. / 1l, this purpose uses logic elements 7 and 8, the inputs of which are connected to the outputs of the memory elements b and the outputs of the reversible counter 9, the logic element 8 performs the logical function 1-C where is the content of (i +1) -6 6 bits in the binary representation of the voltage to be converted, 1 is the number written in the reversing counter of the counter 9. At the output of logic element 9, a signal appears equal to one if (and) the (most significant) bit is zero. The signal from the output of the logic element 8 is fed to the input of the addition of the reversible counter 9 and increases its content by one, due to which in the next conversion cycle the number of bits decreases by one. Logic element 7 performs a logical function, i-n where X j. - the contents of the K-th bit aatv of the original number; 3 - chkspo recorded in the reverse counter 9; m is the maximum number of bits of a binary number; P - a logical product. Consequently, if in all bits, beginning with (d + 1), units are contained, then the output of logic element 7 will produce a signal / which feeds to the subtraction input of the reversible counter 9, and in the next clock cycle npeia6razov the number of bits increases per unit, which allows the signal to be converted twice as large as the previous one in absolute value, i.e. The proposed device monitors exponentially fast signal changes. Not all 1Aprays, but only (m-i) bits go to the communication channel, since the first L bits are turned off and their contents are zero. Since the change in the number of bits is based on the analysis of a binary number, the priority

given over the communication channel in the next clock cycle, then at the receiving end, by a similar analysis, determine the number of bits that are transmitted at the next clock cycle.

Claims (1)

1. USSR author's certificate No. 293239, cl. GO6 F 5 / O2, 07.03.69. S. Shl npin V. M. Digital electrical measuring instruments, M., Energie, 1972, p. 282, fig. 7-1.