SU1285483A1 - Device for generating tests for diagnostic checking of discrete units - Google Patents

Abstract

The invention relates to computing and may be non-. used to form pseudo-random tests in the systems of control and diagnostics of discrete blocks. The aim of the invention is to reduce the completeness of the dough being formed by increasing the completeness of the coating k subterms: the trivial tests are equivalent to the inputs of an n-input controlled circuit. Set The device contains a clock generator, an n-bit shift register, an i (k-1) input element ISH-NOT, a unit of recalculation based on the variable module, a unit for generating a feedback function. The recalculation block by the modulated module contains a D-trigger, a master of the recalculation module, a binary counter, a comparator and a delay element. The block forming the feedback function contains a node of a fixed memory, a group of (k-1) elements And and (k + 1) - an input modulo two, due to the fact that in the process of forming pseudo-random tests in the device modifying the connections of the modulo-two inputs with the shift register outputs provides increased completeness of the test being formed, which is defined as the ratio of the number of subsets of k outputs where all possible binary combinations appear to the total number of subsets of k outputs. 2 hp f-ly, 3 ill. with s (/) C

Description

The invention relates to computing and can be used to form pseudo-random tests in monitoring and diagnostic systems for discrete blocks.

The purpose of the invention is to increase the completeness of the molded dough.

FIG. 1 shows a block diagram of the device; in fig. 2 and 3 are functional diagrams, respectively, of the Modulo recalculation block for the modified module and the feedback function generator unit.

The device (Fig. 1) contains a clock generator 1, an n-bit shift register 2, (K-1) input element OR-NO 3, a conversion module A using a variable module, a feedback function generation unit 5.

The recalculation unit 4 according to the modulated module (Fig. 2) contains a D-flip-flop 6, a setting device 7 of the recalculation module, a binary counter 8, a comparator 9 and a delay 10 of a binary.

The feedback function forming unit 5 (FIG. 3) contains a node 11 of the Permanent memory, a group of (k-1) AND 12 elements and (k + 1) -BXO-type adder 13 modulo two.

The device works as follows.

For each clock pulse, information in register 2 is shifted by one bit towards the higher bits. At the same time, the k lower-order bits of register 2 operate as a k-bit register with fixed feedback. Upon reaching k the youngest bits of register 2 of state 00 ... 01, where the only unit is in (kl) -M bit, a single signal is produced at the output of the OR-NO 3 element, as a result of which the signals at the output of the conversion unit 4 change modifiable module, and ,. accordingly, the feedback function generated in block 5 is changed. A single signal coming from an OR-NOT 3 element to the first input of the function formation and feedback block 5 provides a zero signal at the output of block 5, and in the next cycle the lower bits of register 2 go to the state 000 ... O. A single signal at the output of the YLI-NOT 3 element is saved, a single signal is generated at the output of block 5, and in the next cycle, the lower bits of register 2 go to the 100 ... O state, after which the output of the OR-NO 3 element is zeroed and The lower order bits of register 2 continue to operate with the new feedback function.

Unit 4 recalculation of the modifiable module works as follows.

The recalculation module of block 4 is equal to the moving code at the output of the setter 7. For each pulse at the input of the block, the contents of counter 8 are incremented by one, and, accordingly, the code at the output of the whole block 4 is increased. At the same time, if counter 8 has not reached the state equal to (the recalculation module, the output of the comparator 9 remains zero, and, accordingly, the trigger 6 is in the zero state. As soon as the state of the counter 8 is compared with the recalculation module, the output signal of the comparator 9 becomes unity and on the next input pulse ode this unit causes the appearance of a single unit pulse at the output latch 6, the duration of which is determined by the element 10 zaderzkki. By this pulse counter 8 is reset to zero and then starts counting again.

The feedback function generating unit 5 operates as follows.

In accordance with the code arriving at the address inputs of node 11 (ROM) forming the first group of block inputs, a (k-1) -discharge code is generated at the outputs of the ROM. This code completely determines the feedback function, namely if in the i-th code bit one, then the corresponding element And 12 is open and the signal at the i-th I input from the second group of block inputs is included in the feedback function. Otherwise (when in the i-th code bit zero) the corresponding elm And 12 is closed and the signal at the i-th input from the second group of block inputs does not affect the feedback function, the signals passing through the elements i, and also, the signals at the first and second inputs of the block are summed at the adder 13 and are output. The presence of the second input of the adder 13 ensures that the signal from the k-ro output of the register 2 is continuously included in the feedback function. Availability per31

The input of the adder 13 provides a modification of the feedback function at the state of the lower-order bits of the register 000 ... 1 in order to reach the state 00 ... O, which is unattainable for the shift register with the unmodifiable linear feedback function zi

The completeness of the formed dough can be defined as the ratio of the number

the subsets of the k outputs, on which all possible binary combinations appear, to the total number of subsets of k extras. Then the completeness of testing using the proposed device will be 1- (1-1) e / that, where m is the recalculation module of block 4, and е is the base of natural logarithms. At that 15, the completeness of the test will be 99.9%. ,

Claims (3)

1. A device for generating diagnostic tests of discrete blocks, containing a clock generator, n is the decoupling shift register, where; n is the maximum number of inputs of monitored blocks, and (k-1) is an input element OR NOT, where PZ-k, and the output of the clock generator is connected to the synchronous input of the n-bit shift register, the outputs of which are the outputs of the device, the outputs of the n-bit shift register c. the first in (k-1) -and connected to the inputs of the (k-1) input element OR-NOT, in order to increase the completeness of the test being formed, the device contains a recalculation unit based on the modifiable module and a feedback function generating unit , moreover, the input of the recalculation unit r to the changeable module is connected to the output home (and-1) input element OR NOT memory, whose address inputs and outputs with the first group of inputs form the first group of inputs of the block, the feedback function forming unit, the first input, the second input and the high inputs of the elements And the groups form the second group of block inputs. 0 five 0 five 0 the stroke of which is connected respectively to the output of the (k-1) input element OR NOT, to the kM output and the information input of the p-bit shifting register; the second group of inputs of the feedback function generating unit is connected to the group of codes from the first on (k-1) -and n-bit shift register. 2. The device according to claim 1, characterized in that the conversion unit for the modulated module contains a setting unit of the conversion unit, D-trigger, a delay element, a binary counter and a comparator, the set of outputs of the setter. The conversion unit is connected to the first group of inputs, comparator The second group of inputs of which is connected to the group of outputs of the counter, which is a group of information outputs of the block, the input of the block is connected to the synchronous inputs of the D-flip-flop and a binary counter, the reset input of which is connected to the output of the D-flip-flop and the input of the element ki, an output connected to the reset input of flip-flop P having an information input coupled to vrsodom comparator. 3. The device according to claim 1, characterized in that the block forming the feedback function comprises a fixed memory node, a group of k-1 elements AND and () an input modulo two, the first and the second inputs and output of which are respectively the first and second inputs and output of the block, the remaining inputs of the (k + 1) -modal modulo adder two are connected to the outputs of the corresponding elements AND groups, the first inputs of which are connected to the corresponding outputs of the node constant n0 memory, the address inputs of which form the first group of block inputs, The second inputs of the AND elements of the group form the second group of inputs of the block. f (k- K-2 H f { // ABOUT / J