SU1755293A1 - Simulator of communication discrete channel - Google Patents

Abstract

The invention relates to radio engineering and can be used to analyze the noise immunity of discrete information transmission systems. The aim of the invention is to expand the functionality of the device by simulating the bi-binary discrete communication channels. To achieve this goal, memory blocks, threshold adders, two code analyzers, an encoder, an adder, and a unitary code to binary converter and a register are entered into the simulator. 5 il.

Description

The invention relates to radio engineering and can be used to analyze the noise immunity of discrete information transmission systems.

A discrete communication channel simulator is known comprising a modulo-two adder, a synchronization unit, a Markov sequential generator, a random number sensor, an intermediate memory block, a threshold adder, and an And element,

A disadvantage of the known device is the inability to simulate the error flow in asymmetric communication channels.

The closest to the claimed is a discrete communication channel simulator containing a modulo two adder, a synchronization unit, a Markov sequence generator, a random number sensor, an intermediate memory block, a threshold adder, and element I.

The disadvantage of the prototype is the narrow functionality that does not allow simulating non-binary discrete communication channels.

The aim of the invention is to expand the functionality of the device by simulating non-binary discrete communication channels.

The goal is achieved by the fact that a discrete communication channel simulator containing a synchronization unit, a Markov sequence generator, a first threshold adder, a random number sensor, the output of a synchronization unit connected to a synchronization input of a Markov sequence generator, the clock output of which is connected to a clock input of a block synchronization, the first output of the clock of the Markov sequence generator is connected to the synchronization input of the random number sensor,

the output group of which is connected to the first group of corresponding information inputs of the first threshold adder, the second group of information inputs of which are connected to the group of corresponding outputs of the first memory block, the trigger input of the synchronization block is the device start input, K-2 memory blocks are inserted, K-2 threshold adders, where K is the base of the signal code, first and second code analyzers, encoder, adder, unitary-to-binary converter, register, and the input of the first code analyzer and output is The second code analyzer and the output of the second code analyzer are respectively the information input and output of the device, the output group of the first code analyzer is connected to the group of corresponding information inputs of the encoder, the output group of which is connected to the first group of corresponding information inputs of the adder and to the first groups of corresponding information inputs of all blocks memory, to the second group of information-C1-of the inputs of each of which is connected a group of the corresponding outputs of the Markov generator sequence, the group of outputs of each of 2 to K-1 memory blocks is connected to the second group of information inputs of the respective threshold adders, the first groups of information inputs of which are connected to the group of the corresponding outputs of the random number sensor, the output of each of the threshold adders is connected to the corresponding information input of the unitary converter code in binary, the output group of which is connected to the second group of the corresponding information inputs of the adder, the output group of which is connected Yuchena to the corresponding information inputs of the register, the group of outputs of which is connected to the group of the corresponding information inputs of the second code analyzer, the second output of the clock pulses of the Markov sequence generator is connected to the control input of the register.

FIG. 1 shows a block diagram of a discrete communication channel simulator; in fig. 2 is a block diagram of a Markov sequence generator; in fig. 3 - block diagram of the first code analyzer; in fig. 4 is a block diagram of a second code analyzer; in fig. 5 is a block diagram of the converter unitary code into binary.

The discrete channel simulator contains a block 1 synchronization generator 2

Markov sequence, memory block 3i Sq-1, threshold adders 4i-4 "-i, sensor 5 random numbers, binary code to unitary converter, first analyzer 7 code, encoder 8, adder 9, register 10 and second 11 code analyzer , the first output of 12 clock pulses, the output of 13 clock pulses and the second output of 14 clock pulses of the generator 2.

0 The generator of the Markov sequence 2 (Fig. 2) contains the first and second delay elements 15 and 16, the register 17, the adder 18, the analog-to-digital converter 19, the 20 clock pulse generator and

5 generator 21 random signal. The first code analyzer 7 (Fig. 3} contains mastodete detectors 22- | -22k. The second code analyzer 11 contains (FIG. 4) generators 231 + 23k, keys 241-24k, summing up the amplifier 25 and decoder 26. Converter 6 unitary code in binary contains (Fig. 5) elements HF 27- | -27k-1, elements And 28i-28x-i and the encoder 9.

The device operates as follows.

It is based on the imitation of the K-th discrete communication channel (as an example, Figs. 3 and 4 illustrate an embodiment of a frequency-manipulated myoscope signal). The signal sign at the input of the simulator with a given stochastic regularities is converted at the output to a tog or other sign of the signal, which simulates the error of different types in

5th communication channel.

After start-up, unit 1 starts working, which periodically starts generator 2, which operates as follows (Fig. 2). The start signal from block 1 and

0 clock pulses from block 20 in block 19, the digital equivalent of the signal generated by block 21 is formed. Blocks 19 and 2 I are configured so that the generated ones are in the range from -1 to -M, with the highest

The 5th digit of the number formed in block 19 is significant. The generated number is algebraically summed with the contents of register 17 in block 18 and some delay determined by element 15 is again transferred to register 17. Thus, a Markov number sequence is generated, in which each successive number depends on the previous one. Separate output from block 17 to block 19 5 is the sign bit output.

After determining the next state of the Markov circuit, the generator 2 generates at the outputs of the register a state code that sets the lower bits of the cells in the memory blocks 3 (the group of lower address bits). The higher bits of the cell address are determined by the input information supplied to block 7. When a certain value of a signal feature (a certain signal frequency) arrives, the corresponding frequency detector is triggered (with frequency manipulation, taken as an example). The set of signals from the output of block 7, which is a unitary code containing among the K bits, a single unit, whose place in the code word corresponds to the number of the activated detector of block 7, is fed to an encoder that converts the unitary code to binary. This code serves to set the higher address bits of memory blocks 3. Thus, the selection of memory cells in blocks 3, determined by the current state of the Markov circuit and by the current value of the signal feature, is realized. In the cells of memory blocks 3, numbers are written that determine the probabilities of transformation of the information signal values. These probability values are formed by the user as follows: in the cells of Block Z-1, binary crushed numbers are written corresponding to the probabilities of transforming the 1st value of the signal feature into the E-1 value (modulo K-1, which is significant for all memory blocks). and their cells) for a given Markov sequence state given by the corresponding address bits. Denote this probability by P (i).

In the cells of the memory block 3k-2, binary numbers corresponding to the sum of probabilities P (i -H + 1) and P (i-i + 2) are written in the same way. Similarly, for cells of memory block 3) (I 1, K-1), numbers for the corresponding states of the Markov chain are

K -I

I) j i

however, all i, j and i + j are determined modulo the number K-1,

The numbers recorded in this way in the cells of memory blocks 3 and selected by codes on the address inputs of blocks 3 arrive at the first inputs of the respective threshold adders, which compare the sum of numbers from the corresponding block 3 and block 5 with the unit and form a single signal when the sum exceeds one (note that the random number generator generates binary numbers in the range from 0 to +1, distributed according to a uniform law). If one term is a uniformly distributed random number, then the probability

the formation of a single signal at the output of the threshold adder is completely determined by the value of another term, namely the probability of error in a certain state of the discrete communication channel.

In accordance with the principle of forming numbers in memory blocks 3, the set of signals from the outputs of adders 4 is in any case a type code 0 ... 01 ... 1, where the units correspond to the values of signals from the outputs of adders 4 with lower indices (they are are triggered earlier because the meanings of the probabilities

is greater than the adder index) This unitary code is converted on elements 27 and 28 into a code with a single unit, which enters encoder 29 completely identical to block 5, if there are units from the inputs, respectively, elements 28i and to the input 27k-h on the outputs of the block 29, numbers from O to K-1 are formed.

The binary number from the output of block 6 is summed (modulo K-1) with the number from block 8 in

block 9. A signal (with a delay determined by element 16} triggers a register 10 into which the sum value (equal to the number of the signal characteristic generated by the simulator is written. The formation (according to the example of multi-frequency manipulation illustrated in Fig. 4) is performed as way. Descrambler 26 converts the binary code into a code with a single unit, opening the corresponding key 24, and the signal with the desired value of the signal sign generated by the block 23 through the summing amplifier 25 is fed to the output simulator.

Thus, the device makes it possible to simulate K-e discrete communication channels with error streams characterized by Markov sequences, which is a more general case than similar ones.

binary Markov channels.

Claims (1)

The invention Discrete channel simulator containing a synchronization unit, a generator Markov sequence, the first threshold adder, random number sensor, the output of the synchronization unit is connected to the synchronization input of the Markov sequence generator, the clock output of which is connected to the clock input of the synchronization unit, the first sync pulse output of the Markov sequence generator is connected to the synchronization input of the random number sensor, group of outputs which is connected to The first group of corresponding information inputs of the first threshold adder, the second group of information inputs of which are connected to the group of corresponding outputs of the first memory block, the trigger input of the synchronization block is a device trigger input, characterized in that, in order to expand the functionality of the device by simulating non-binary discrete communication channels, K-2 memory blocks, K-2 threshold adders are entered into it, where K is the base of the signal code, the first and second code analyzers, the encoder, an adder, a unitary code to binary converter, a register, the input of the first code analyzer and the output of the second code analyzer are respectively the information input and the device output, the output group of the first code analyzer is connected to the group of corresponding information inputs of the encoder, the group of outputs of which is connected to the first group of corresponding information inputs of the adder and to the first groups of corresponding information inputs of all memory blocks, to the second groups of information inputs of each of which is connected a group of corresponding outputs of the Markov sequence generator. the group of outputs of each from the second to K-l memory blocks is connected to the second group of information inputs of the corresponding threshold adder, the first groups of information inputs of all threshold adders are connected to a group of corresponding outputs of the random number sensor, the output of each of the threshold adders is connected to the corresponding information input of the converter unitary code in binary, the output group of which is connected to the second group of the corresponding information inputs of the adder, the output group of which is connected to the corresponding information inputs of the register, the output group of which is connected to the group of the corresponding information inputs of the second code analyzer, the second output of the Markov clock sync pulses the sequence is connected to the control inputs of the register. 17 R t I BUT J 71 one il year FIG E pv 2 IA .arj Sh..vZh // FIG. four zi n L, 41ad Rich.