SU1249541A1 - Device for determining centre of mass of flat figure - Google Patents

Abstract

The device relates to computing technology and can be used in digital signal processing systems, determine the sum of samples of the input signal, and normalizes it to the sum of samples. The purpose of the invention is to increase speed. The device contains ring counters, registers, logic elements, memory block, switches. 1 il. and with 4 QD SL

Description

The invention relates to computing and can be used in digital signal processing systems for various purposes to form probabilistic characteristics of random processes, in particular, to determine the center of mass of flat figures.

The purpose of the invention is to increase the speed of the device

The drawing shows a block diagram of the device.

The device contains a setup input, an information input, and the operation of the device is provided by control signals: set 1, offset .2, clock 3, record 4, summation 5, census 6, coming respectively from the synchronizer outputs of the same name 7; input 8 of the device correction constant, N-bit shift register 9, where N is the number of samples of the input signal (for definiteness N is assumed odd), input register 10, the first switch 11, register 12 of the sum of samples of the input signal, the first 13 and the second 14 ring counters, first adder 15, memory block 16, first 17 and second 18 triggers, second switch 19, multiplication unit 20, OR-NOT 21 element, OR element 22, counter 23, second adder 24 and device output 2,

The nets 13 and 14 perform the role of delay elements by n + 1 cycles.

(p-0 I - 1, by xj denoted

the whole part of the real number is x). Accordingly, their size is (n + 1) bits. The input j-ro bit (J 0,1 ,,. ,, n-1) ring counter 13 is connected to the output j-ro bit of the shift register 9, and the input (J + 1) -th bit of the ring counter 14 is connected to the output (n + j + 1) -ro of the shift register 9. The outputs of the higher discharge of the ring counter 13 and the lower bit of the ring counter 14 are connected to the single inputs of the trigger 1 and 18, respectively, the counting codes of counters 13 and 14 are combined and 3 synchronizers are connected to the output of the control inputs of the reception of the counter code 13 and 14, the input register 10, zero inputs of the trigger 17 and 18 of the volume

5 0 5 0 j

five

five

dinene and connected to the output 4 of the synchronizer 7 device.

The zero-bit output of register 9 is connected to the reset inputs of register 12 and counter 23, and the output of the (n-1) -th bit is connected to the second input of element 22, the first input of which is combined with the single trigger input (7, and the output is connected to the control input of the switch 19 and the counting input of the counter 23. The outputs of the flip-flops 17 and 18 are connected respectively to the second and third inputs of the OR-NOT 21 element, the output connected to the control input of the receiving code of the counter 23.

The adder 15 performs the addition of binary numbers modulo 2, where

B log, (n (n-f1) ()),

where bo is the VHBD ™ sample count

signal, denoted by Jx. denotes the smallest integer, not less than x. Accordingly, the switches 11 and 19 each contain two dual-channel multiplexers on the L-d channel, and the resolution of the registers 10 and 12 and the counter 23 is the b bit.

The control unit of the switch 11 is connected to the output 5 of the synchronizer, the first information input of the switch 11 is combined with the second input of the multiplication unit 20 and connected to the output of the counter 23. The second information input of the switch 11 is combined with the input of the memory block 16 and connected to the output of the register 12, the input control reception code of which is combined with the first input of the element OR NOT 21 and I is connected to the output 6 of the synchronizer, the output of the switch 11 is connected to the second input of the adder 15, the first input of the connected input to the output of the register 10. The first input the formation input of the switch 19 is combined with the information input of the register 12 and connected to the forward output of the adder 15. The second information input is connected to the inverse output of the adder 15, and the output to the information input of the counter 23.

The memory block 16 has a capacity of 2 words of the bit size b () bits. In memory at Be 1,2, ...,

-1 write constant

g 1 q (B) S-2 .., (,)

3

where b log, N () /, S is the whole positive scale, the bit size of which is bj bits, x is the integer nearest to X, i.e.

one

x, if - x, if x + -4:

The multiplication unit 20 serves for half-output on -2V1, -2 + 2, ..., 2 - 1J presented in the additional code. The first input of block 20 is connected to the output of memory block 16, and the output of the group of bits, starting from (L. -1) -th to (2) -th, is connected to the first input of the second adder 24, implementing the addition operation modulo 2 where

B, / (n + 1) () /.

The second input of the second adder 24 is connected to the input 8 of the correction constant, and the output is the output 25 of the device.

The function of the proposed device for determining the center of mass of a flat figure is to calculate the magnitude

1 X

f S (2)

tm

where S is the positive integer scale, x is the i-th count of the input signal, 1, ..., bo-l.

Adding and subtracting in the right part of (2) the value of (n + 1) S, the characteristic jy can be represented as

f - + (n + 1.) - S,

(3)

A-J:: (p-1 + 1) x, + (4)

l / z: -h ..

i:

(five)

According to the modified Euclidean theorem of the divisibility theorem, we can write down:

S + Q (B) -B, (6)

1249541

- | where (S 2 1 is the absolutely smallest deduction comparable to the value modulo B, Q (B) is the value determined by the relation (1). Substituting (6) into (3), we find:

p- 5ji i- -f.,

-,

Q

Since | AU, and

42

then the first sentence in the last

ratio does not exceed 1/2. Pre-15 them, we obtain the following calculated ratio for the desired characteristic:

20

f-f + (. (7)

The device works as follows.

The processing of samples of a separate implementation of a random process carrying information about the observed object is carried out in two stages. The first stage takes N cycles, the i-th of which correspond to the counting x - (, 2, ..., N): at the same time, similar actions are performed on each cycle during n + 1 cycles.

Before the first cycle, the unit code is written to the shift register 9 through the installation output 1 of the synchronizer, the contents of the zero bit of register 9 (about 1) are fed to the reset inputs of the register 12 and counter 23, as a result of which they are zeroed. In the first cycle of the first cycle, the signal Gg 1, coming from the output 4 of the synchronizer, reads x into the input register 10, and the contents of the low and high bits of register 9 are transmitted to the ring counters 13 via the information input of the device. and 14, and triggers 17 and 18 are zeroed. Then, the first and second information inputs of the switch 11 are fed respectively to the contents of the counter 23 and register 12 (currently zero), and the control output of the synchronizer 5 is supplied with a signal G, 1, so that the output of the switch 11

register 12 appears, which is fed to the second input of the adder 15. At its first input from the output of register 10, a countdown is given

X. as a result, the adder 15 will receive a value .O, which is received from the first direct output of the adder 15. It is connected to the first information input of the switch 19 and is written to the register 12 by the signal Gu 1 supplied to its control input 6 of the synchronizer. The inverse code of x + 1 from the second (inverse) output of the adder 15 is fed to the second information input of the switch 19, to the control input of which a signal is applied

12495416

the adder 15 through the first information input of the switch t1 will enter the contents of the counter 23, i.e. the value of (j-1) x. By folding the contents of X, the input register 10 and the number (j-1) x, the adder 15 will receive the value through the first informant jx,

The input of the switch 19 is transferred to the counter 23. To the input of the control 1.10, the switch 19 and the control input for receiving the counter code 23 in the considered cycle, respectively, receive signals: Г 0, Т 1. Thus, upon completion

G, Y „„ ,,

(eight)

produced by the element And 22 according to the input values 6 and 6 ,. , arriving respectively from the outputs of the n-th bit of the ring counter 13 and (n-l) -ro bit of the shift register 9. At a given clock rate Tj O, therefore, the output of the switch 19 shows the value fed to its information input. The code formed at the switch 19 output goes to the information input of the counter 23j, however, it will not be recorded, since the control input of the code reception of the counter 23 from the output of the ORID 21 signal is given

Fg r Vr - Vr

(9)

accepting a zero value, due to the fact that the first input of the element, WDI-NOT 21, is sent from the sixth output of the synchronizer signal G. 1. (r and d are the contents of the triggers 17 and 18, respectively).

At the end of each cycle, according to the signal supplied from the output 3 of the synchronizer to the counting inputs of the ring counters 13 and 14, their contents are shifted respectively 1.bit to the left and 1 bit to the right. The advanced values 6 and 6 of the high and low bits of the ring counters 13 and 14 are applied to the single inputs of the flip-flops 17 and 18, respectively.

On the subsequent five cycles of the device operation cycle, the described actions are repeated, except that the outputs 4, 5 and 6 of the synchronizer do not receive single signals (i.e., G - rj G4 - 0), According to (j + 1) -ro tact of the first cycle (J 1,2, ..., p) to the second input

the adder 15 through the first information input of the switch t1 will enter the contents of the counter 23, i.e. the value of (j-1) x. By folding the contents of X, the input register 10 and the number (j-1) x, the adder 15 will receive the value through the first information

well jx,

The input of the switch 19 is transmitted to the counter 23. The control input of the switch 19 and the control input of the receipt of the counter code 23 in the considered cycle respectively receive signals: D 0, 1. Thus, at the end

The first 12 in the register 12 will form the code of the number x, and in the counter 23 - the code of the number nx.

At the end of each cycle, the signal G 1 supplied from synchronizer output 2, the contents of shift register 9 is shifted 1 bit to the left, and then the next cycle begins, during which the described actions of the device are performed.

On the first cycle of the nth cycle (i - 2,3, ... n), adder 15 receives the sum of the first i samples of the input signal

nald.:;

tact tact

Ejx ,, and it is recorded in re

12, and at the end (n-i + 2) -ro

The i-ro cycle in counter 23 will receive a weighted sum of i signal samples: 23 () х „, At the first

the cycle i-ro of the cycle (i 1,2, ..., p) in the ring counter 13; the unit will be recorded in (i-1) -oM bit. Therefore, after the expiration of (n-i + 2), the unit from the high-order output of the ring counter 13 will also go to the single input of the trigger 17, therefore, to. all subsequent cycles of the cycle, the output signal G of the element. OR-NO 21 takes a zero value (9). This results in blocking the recording of the information I.Jiii into counter 23, i.e. The indicated i-ro cycle times are idle.

In the second cycle of the nth cycle, the first and second inputs of the element and 22 receive single signals (1), so that the control input of the switch 19 and the counting input of the counter 23 will receive a signal Fj 1 (8). As a result, the counter 23 will receive the return code led0 through the second information input of the switch 19.

ranks - 22 (n-i4-1) x J, formed in

dannbm tact inverse output

7

adder 15. After adding the ecs to the counter 23, an additional code of the first term relation (4) is generated. At the end of the N-ro cycle of the device operation, the value of B (5) will be received in register, and the counter 23 will receive an additional code of code A (4), while during the last five cycles the consistency of control signals for writing information to the counter 23 will be swept out using the ring counter 14 and trigger 18.

After calculating the values of A and B, the proposed device can start processing the samples of the new implementation of the process under study. At the same time, the device implements the second stage of the procedure for generating the characteristic Jo (7) for the current implementation of the process. To this end, the value B from the output of register 1 is fed to the address input of memory block 16, where the binary code of the constant Q is read at address B (B ) (1 which, from the output of block 16, is fed to the first input of multiplication unit 20, and to its second input from the output of counter 23, an additional code of number A is supplied. The multiplication unit 20 finds the product AQ (B) and its senior

A: Q (S)

part (whole part of fraction

L, -1

)

enters the first input of the adder 24.35 memory and is connected to the output of the register

the second input 8 of which is supplied with a constant (n + 1) S. By folding the input values, the adder 24 determines the desired characteristic (7). The code of the value of f is removed from the output 25 of the device, and the processing of the current implementation of the initial process ends there.

The proposed device defines

the weighted sum of samples, the input signal and normalizes it to the sum of samples, while it is possible to combine the processing of adjacent realizations of the random process under study in 6 times.

Claims (1)

Formula invented A device for determining the center of mass of a flat figure, containing an input register, the first annular ,eight and 12 to 20 2 25, the counter, the first adder, the first input connected to the output of the input register, the first trigger and the element I, the first input of which is combined with the single input of the first trigger and connected to the output of the higher bit of the first ring counter, in order to increase its speed entered synchronizer, N-pasddny shift register (N is the number of samples of the input signal), the first and second switches, the register of the sum of samples of the input signal, the second 5i ring counter, memory block, second trigger, multiplication unit, el the OR-NOT unit, the counter and the second summer, while the inputs n of the lower bits of the first ring counter (n is the whole part of the N / 2 value) are connected to the outputs of the same bits of the N – discharge shift register, the inputs of the n higher ones The second ring counter is connected respectively to the output n of the higher bits of the shift register, and the low-order output of the second ring counter is connected to the single input of the second trigger, the first information input of the first switch is combined with the second input of the multiplying unit and Connected to the output of the counter, the second information input of the first switch is combined with the input of the unit thirty five 0 five the sum of the input signal counts, and the output is connected to the second input of the first adder, the first information input of the second switch is combined with the input register of the sum of the input signal counts and connected to the forward output of the first adder, the second information input of the second switch is connected to the inverse output of the first adder, and the output - and the information input of the counter, the counting input of which is combined with the control input of the second switch and connected to the output of the element I, the first input of the multiplication unit is connected to the output b memory, and the output to the first input of the second adder, the outputs of the first and second flip-flops are connected respectively to the second and third inputs of the OR-NOT element, the output of which is connected to the control input of the counter code reception, the second input of the AND element is connected to vyd the (nl) -ro bit of the N-bit shift register, whose information input and shift control input are connected to the first and second outputs of the synchronizer, respectively, the zero-bit output of the N-bit shift register is connected to the reset inputs of the sum register of the input signal and the counter, the counting inputs of the ring meters are combined and connected to the third output of the synchronizer, the information input of the input register is the information input of the device, the input of the reception control Compiled by V.Orlov Editor S.Patrusheva Tehred V.Kadar Proofreader M.Demchik Order 4327/51 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 9541 ten , input register code, first and second ring counters, zero trigger inputs are combined and connected to the fourth output of the device synchronizer 5, the control input of the first switch is connected to the synchronizer fifth output, the input control register input code of the sum of samples of the input signal and the first 0 input the element OR is NOT combined and connected to the sixth output of the synchronizer, the second input and the output of the second adder are respectively the input of the correction constant 15 and the output of the device.