SU1141403A1 - Dividing device - Google Patents

Abstract

A DEVICE FOR FISSION, containing an adder, a register of a small amount, a register of bitwise transfer, a register of a divider, a register of positive private numbers, a register of negative private numbers, a control unit and an analyzer containing the element OR, the first and second elements AND, and the element NOT, the first and second information inputs of the adder are connected respectively to the outputs of the registers of the bit-sum and transfer, and the third information input of the adder is connected to the output of the register divider, the information input of which is connected Inen with the input of the device divider, the input of which is divisible is connected to the first information input of the register of the bit amount, the second information input of which is connected to the code of the sum total of the adder. the bit-wise output of which is connected to the bit-transfer register information input, the low-level transfer bit input, the mat is connected to the control input of issuing the delimiter's return code, the control input of the bit-sum register code is connected to the control input input the bit transfer register code and with the first control output of the control unit, the second control output of which is connected to the shift inputs of the registers of the positive and negative digits of the private, the outputs of which are connected Inen respectively (L with the first and second drives of the device, the Start input and the Output of the Operation end of which are connected respectively to the Start input and the output. End of operation of the control unit, characterized in that, in order to improve speed, 4 analysis, which contains the first, second, third and fourth elements OR, first, second, third, about the fourth, fifth elements of NOT, first, 00 second, third, fourth, fifth, sixth, seventh, eighth elements And, first and second triggers, and in the block In the analysis mode, the output of the first trigger is connected to the first input of the second OR element and to the third input of the first element AND, the second input of which is connected to the first input of the second element AND and to the output of the second trigger, the unit installation input of which is connected to the output of the eighth element AND, first input

Description

which is connected to the output of the fourth OR element, the first input of which is connected to the output of the sixth AND element, the first input of which is connected to the second input of the third OR element and to the output of the fifth NO element, the input of which is connected to the output of the second OR element, the installation input of the unit of the first trigger connected to the code of the seventh element AND, the first input of which is connected to the output of the third element OR, the first input of which is connected to the output of the fifth element AND, three inputs of which are connected respectively to the outputs of the first, second O and the third element IE, the input of the first element is NOT connected to the first input of the third element I, the second input of which is connected to the second input of the first OR element, the output of which is connected to the fourth input of the fourth AND element, the first input of which is connected to the second input of the sixth element And with the output of the fourth element is NOT, the input of which is connected to the output of the third element And, the output of the first element And is connected to the input of the third element NOT, the outputs of the second and fourth elements And are connected respectively to the second inputs of the second second and fourth elements OR, the second inputs of the seventh and eighth elements And connected to the third control output of the control unit, the fourth control output of which is connected to the inputs of the zero setting of the first and second triggers And the first and second inputs of the first and second elements And respectively connected to the output transfer to the character bit of the adder, the analyzer contains the second, third, fourth, five elements OR, the third, fourth elements AND, the first and second triggers, and in the analyzer the outputs of the trigger Ina with the control inputs of the forward and reverse divider register codes, respectively, the installation input of the unit of the first trigger is connected to the information input of the register negative of the quotient and with the output of the NOT element whose input is connected to the output of the fourth element And, first, second, third, fourth the inputs of which are connected respectively

with the outputs of the first, second, third, fourth OR elements, input {setting the unit of the second trigger soi; inn with the information input of the register of positive digits of the private and with the output of the fifth element OR, the first, second, third inputs of which are connected respectively to the outputs of the first, second and the third element AND, the third input of the third element AND is connected to the output of the first element OR of the determination block of the ana mode, the output of the second element OR of which is connected to the second input of the fourth element OR, the third input of the second the AND element and the fourth input of the third element AND of the analyzer, the first input of the first element AND of which is connected to the third input of the third element OR, the fourth inputs of the first and second element OR of the analyzer and the output of the first element AND the analysis mode determination unit, the first control output of the control unit connected to the inputs of the zero setting of the first and second triggers, the second input of the first element AND, the fourth and fifth inputs of the second and third elements AND of the analyzer, the fifth inputs of the first and second elements OR which connected to the first input of the fourth OR element, the fourth input of the third IL, analyzer and the fifth control output of the control unit; the first inputs of the first and second OR elements and the third element AND of the analyzer are connected to the second input of the fourth element AND the output of the second most significant bit of the transfer of the adder, the output of the first most significant bit of the transfer of which is connected to the third input of the first OR element, the second input of the tpeTbero element OR, the second input of the second element AND and the first input of the first element OR for determining the analysis mode, the input of the second element is NOT connected to the third input of the second element OR, the first input of the third element OR, the first input of the second element AND of the analyzer and the output of the first most significant sum of the adder, the output of the second most significant the digit of the sum of which is connected to the second inputs of the first and

the second element OR and the third element AND of the analyzer and with the third input of the fourth element AND the block determining the analysis mode, in addition, the control unit contains a signal generator, trigger work, a counter., the analyzer is zero, the first and second elements are NOT, the first, second and the third elements And, the first, second, third and fourth elements of the delay; in the control unit, the input The start of the control unit is connected to the installation input of the trigger unit and the clock input of the counter, the counting input of which is connected to the first output of the control unit , The input of the second delay element and the output of the first delay element whose input is connected to the input of the second element NOT and the output of the first element And, the second input of which is connected to the output of the work trigger and the first input of the second element And, the third input of which is connected to you

the signal generator and the third input of the first element And, the first input of which is connected to the first input of the third element And the output of the first element NOT, the input of which is connected to the second input of the second element And the output of the analyzer zero, the input of which is connected to the output of the counter, the input setting the zero trigger of operation is connected to the output of the second element I and to the output The end of the operation of the control unit, the second output of which is connected to the output of the third element I, the second input of which is connected to the output of the fourth delay element whose input is connected to the fourth output of the control unit and the output of the third Delay element, the input of which is connected to the output of the second delay element and the third output of the control unit, the fifth output of which is connected to the output of the first HE element.

one

The invention relates to computing technology.

A division device containing counters of the dividend, divider and result, the first and second counters, a switch, two control keys, two pulse drivers, a trigger and an AND CO element are known.

The disadvantage of the device is low speed.

A device for multiplying and dividing a series-parallel action is known, comprising a converter of digits of a multiplicand (divisor) into a single code, a reversible counter of digits of a multiplier (divisor), a reversible counter of a product (divisible), a trigger for reversing the product, P groups (t is the operands) elements AND and OR C2j.

The disadvantage of this device is low speed.

The closest in technical essence to the proposed device is a dividing device, containing an adder, a register of bit sums, a register of bitwise transfers,

Shift register of positive digits of quotient Shift register of negative digits of quotient, control block, additional adder, code analyzer of high-order residual bits, information inputs of the dividend and divisor, control input of start 5, control output of the end of operation, information outputs of codes of positive and negative digits

and informational

private

the input of the code of the first adder is connected to the information output of the register a bit of the sum, the first and second information inputs of which are connected respectively to the information input of the dividend dividing device and the output of the sum cyMNjaTopa, the second information input of which is connected to the information output of the bit register transfer, information input connected to the transfer information output of the adder, the third information input of which is connected to the information output register deli ate informagdionnym

the input of the splitter divider connected to the information input, the start input of which is connected to the start input of the control unit, the first, second and third outputs of which are connected respectively to the control input of the high-end bit code analyzer to the control inputs for receiving code of partial amount sums and transfer and to the control inputs of the shift of the registers of positive and negative digits of the private, information outputs connected respectively to the information output of the w codes of positive and negative Private digits of the first and second bit informational inputs of the additional adder are connected to the output of the upper bits of the bit transfer register and the bit register, the inputs of which are located in the additional bits of the additional adder, the input of the code analyzer of the remaining bits of the remainder is connected to output of the high bits of the register of the bit amount, output 1 of the code analyzer of the high bits of the remainder - to the control input of the reverse code of the register of the divider, to the input +1 in the lower bit of the adder and-to i dy +1 register pololsitepnyh private numbers, yield -1 Sodin analyzer with an entrance vschachi direct code register divider, the output end of the device operation dividing connected to the output end of operation control bl.oka.

A feature of the dividing device is that the formation of the residual is carried out in the form of a two-bit code of bitwise transfer and transfer (without distribution of transfers among bits) 3.

A disadvantage of the known dividing devices is the large delays in the formation of the residual sign with significant equipment costs.

The purpose of the invention is to increase the speed and reduce hardware costs.

The goal is achieved by the fact that the division device containing an adder, a bit amount register, a bit transfer register, a divisor register, a control unit, and a positive register

private numbers, a register of negative private numbers and an analyzer containing the elements OR, the first and second elements AND and the element NOT, the first and second information inputs of the adder are connected to the outputs of the one-bit amount and transfer registers, and the third information input of the adder - to the output the register of the divider, informational information of which is connected to the input of the device divider, the input of the dividend connected to the first information input of the register of the partial amount, the second information input

which is connected to the output at once.

the sum of the adder, the output of the bit transfer connected to the information input of the register of bit transfer, the transfer input of the low-order bit of the adder is connected to the second control input of the reverse code of the register of the divider, the control input of the code of the register of the bit amount - with the control input receiving the code of the bitwise transfer register and with the first control output of the control unit, the second control output connected to the shift inputs of the registers of the positive and negative digits of the private, the outputs to which are connected respectively with the first and second outputs of the device, Start input and output whose end of operation is connected, respectively, to the Start input and the output End of operation of the control unit, an analysis mode determination unit is inserted, which contains the first, second, third and fourth elements OR , the first, second, third, fourth and fifth elements are NOT, the first, second, third, fourth, fifth, sixth, seventh and eighth elements are AND, the first and second triggers, and in the block for determining the analysis mode the output of the first trigger is connected to the first m input of the second element OR and the third input of the first element AND, the second input of which is connected to the first input of the second element AND and the output of the second trigger, installation input, the unit connected to the output of the eighth element AND, the first input of which is connected to the output of the fourth element OR , the first input of the sixth element AND connected to the output, the first input of which is connected to the second input of the third OR element and the output of the fifth element NOT, the input connected to the output of the second OR element, the installation input of the unit of the first m igger is connected to the output of the seventh And element, the first input of which is connected to the output of the third element —OR, the first input of the And element connected to the output, the three inputs of which are connected respectively to the outputs of the first, second and third elements, the first element is NOT to the first the input of the third element AND the second input of which is connected to the second input of the first element OR, the output connected to the fourth input of the fourth element AND, the first input of which is connected to the second input of the sixth element AND and to the output of the fourth the element NO, the input of the third element AND connected to the output, the output of the first element AND is connected to the input of the third element NOT, the outputs of the second and fourth elements AND, respectively, with the second inputs of the second and fourth elements OR, the second moves of the seventh and eighth elements AND - with the third control output of the control unit, the fourth control output of which is connected to the installation inputs of the first and second triggers; the first and second inputs of the first and second I elements - respectively, with the transfer output to the sign bit The adder, the analyzer additionally contains the second, third, fourth and fifth elements OR, the third fourth elements AND, the first and the second, triggers, and in the torus analysis, the trigger outputs are connected to the first and second control inputs of the divider, respectively, the units of the first trigger - with the information input of the register of negative digits of the quotient and .c output of the NOT element, the input of which is connected to the output of the fourth And element, the first, second, third and fourth inputs of the connected, respectively, with the outputs the first, second, third and fourth elements OR, the installation of the unit installation of the second trigger is connected to the information input of the register of positive private digit and with the output of the fifth element of the FDI, the first, second and third inputs of which are connected respectively to the outputs of the first, second and third elements AND , the third input of the third element AND with the output of the first element OR of the analysis mode determination unit, the output of the second element of the IPD of which is connected to the second input of the fourth element OR, the third input of the second element AND and the fourth the third input of the third element AND analyzer, the first input of the first element AND connected to the third input of the third element OR, the fourth inputs of the first and second elements OR of the analyzer and the output of the first element AND block of the analysis mode determining unit, the first control output of the control unit connected to the inputs of the zero setting the first and second triggers, the second input of the first element AND, the fourth and fifth input: the second and third elements AND of the analyzer, the fifth inputs of the first and second elements OR of which are connected to the first input of the fourth element P1LI, the fourth input of the third element OR, the analyzer and the fifth control output of the control unit, the first inputs of the first and second elements OR and the third element AND of the analyzer with the second input of the fourth element And the analysis mode determination unit and the output of the second highest bit yes transfer the adder, the output of the first high bit of the transfer of which is connected to the third input of the first element OR, the second input of the third element OR, the second input of the second element AND of the analyzer and the first input ne element OR of the analysis mode determination unit, the input of the second element NOT connected to the third input of the second OR element, the first input of the third OR element, the input of the second AND element of the analyzer with the output of the first high bit of the sum of the adder, the output of the second high bit of the sum of which is connected to the second inputs of the first and second OR elements and the third element AND of the analyzer and with the third input of the fourth element AND the analysis mode determination unit, wherein the control unit contains a signal generator.

7

operation trigger, counter, analyzer zero, first and second elements NOT, first, second and third elements AND, first, second, third and fourth elements of delay, moreover, in the control unit, the input of the start of the control unit is connected to the installation input of the unit of operation trigger and a clock input of the counter, the counting input of which is connected to the first output of the control unit, the input of the second delay element and the output of the first delay element connected to the input of the second ale. NOT and the output of the first element And, the second input of which is connected to the output of the work trigger and the first input of the second element And, the third input of which is connected to the output

the signal generator and the third input of the first element AND, the first input connected to the first input of the third element AND and the first element NOT, whose input is connected to the second input of the second element AND and the analyzer zero output, the input connected to the output of the counter, the zero setting input the operation trigger is connected to the output of the second element AND and the output. The end of the operation of the control unit, the second output of which. connected to the output of the third element And, the second input of the fourth delay element connected to the output, whose input is connected to the fourth output of the control unit and the output of the third delay element, the input connected to the output of the second delay element and the third output of the control unit, the fifth output of which is connected to the output the first element is NOT,

FIG. 1 shows a block diagram of a dp division device in FIG. 2 and 3, respectively, of the circuit for determining the analysis mode and the analyzer; in fig. 4 is a block diagram of the control unit i in FIG. 5 - times. The diagram of his work.

The device for dividing (Fig. 1) contains adder 1, input 2 transferring low-order bit of adder 1, first information input 3 of adder 1, output 4 of the small amount of adder 1, second information input 5 of adder 1, output b of bitwise transfer of adder 1 , tre038

This information input 7 of the adder 1, the outputs of the higher bits of the bit amount 8 of the adder 1 and the bit transfer of 9 of the adder 1, the output of 10 transfer to the sign bit of the adder 1, the register 11 of the bit amount, the first 12 and the second 13 information inputs of the register 11 , the control input 14 of the reception of the register code 11, the output .15 of the register 11, the register 16 of bitwise transfer, the information input 17 of the register 16, the control input 18 of the reception of the register code 16, the output 19 of the register 16,

motor register 20, information input 21 of register 20, control inputs of forward 22 and reverse 23 register codes 20, output 24 of register 20, control unit 25, input 26

Start-up of unit 25, output 27 End of operations of unit 25, control outputs 28-32 of unit 25, analyzer 33, input 34 of higher transfer bits of the analyzer 33, input 35 of higher

analyzer 33 digits, outputs 36 and 37 of the analyzer 33, control inputs 38 and 39 of the analyzer 33, outputs 40 and 41 of the analyzer 33, inputs 42-44 of the analyzer 33, block

45 determining the analysis mode, the input 46 of the higher transfer bits of block 45, the input of 47 high bits of the sum of block 45, the outputs 48-50 of block 45, control 1e inputs 51 and 52 of block 45,

input 53 of the transfer to the sign bit of block 45, register 54 positive digits of the private, information input 55 of the register 54, input 56 of the register shift 54, output 57 of the register 54, re-.

gist 58 negative digits of the private, input 59 shift register 58, information input 60 register 58, output 61 register 58, input 62. divisible device, input 63 divider device, input 64 Start device,

input 65 End of device operation, first 66. and second 67 device outputs.

Analysis mode determination block

(Fig. 2) contains the first 68, the second 69, the third 70 and the fourth 71 elements OR, the first 72, the second 73, the third 74, the quarter 75 and the fifth 76 elements NOT, the first 77, the second 78,

the third 79, the fourth 80, five 81, the sixth 82, the seventh 83 and the eighth 84 elements And, the first 85 and second 86 triggers, the inputs of the first 87 (Si) 9 and the second 88 (S 2) senior sums of the sum that are two The input bits of the 47 most significant bits of the sum of the analysis mode determination block 45 are the inputs of the second 89 (P2) and third 90 (PZ) higher transfer bits, which are two bits of the input 46 of the old transfer bits of the analysis mode determination unit 45. The analyzer (Fig. 3) contains the first 91, the second 92, the third 93, the fourth 94 and the fifth 95 elements OR, the first 96, the second 97, the third 98 and the fourth 99 elements AND, the element NOT 100, the first 101 and the second 102 trig -15

geres, the inputs of the first 103 (S 1) and the second 104 (32) most significant bits of the sum, which are the two bits of the input of the 3-5 most significant bits of the sum of the analyzer, the inputs of the second 105. (П2) and the third 106 (ПЗ) of the older times ) Transfer IDs, which are the two input bits of the 34 highest transfer bits of the analyzer.

The control unit (Fig. 4) contains a counter 107, a zero analyzer 108, a work trigger 109, a signal generator 110, a first 111 and a second 112 elements NOT, a first 113, a second 114 and a third 115 elements And, a first 116, a second 117, a third 118 and fourth 119 delay elements.

The division is performed on normalized numbers, i.e. the dividend and the divisor must have a unit in the highest bit fractional part. The trends are positive.

The proposed device uses the principle of division, in which the redundant code of the quotient is used. Each private digit can be represented as one of three digits: -1.0 + 1. The remainder is generated in the form of a two-row code, including a one-half sum code and one-bit transfer code.

The analysis of the sign of the remainder is performed directly on the two-row residue code, and only two high-order bits of the fractional part of the bit-sum codes of the 51 52 P2PZ residue balance are analyzed. This takes into account the transfer to sign bit, the type of residue obtained in the previous step, and the analysis mode.

The analysis mode is established on the basis of three signs, the quality of which is used: П1 module units), PUP - pre-accounted transfer (if the transfer, which at the next stage determines the performance) is taken into account when making a decision on the sign in the previous step.

The table shows all possible combinations 5152, П2 ПЗ (column 2) and all permissible combinations of signs of the mode (columns 3-8). Shaded cells correspond to situations that cannot occur because of the impossibility of the appearance of a residue modulo not less than 1. Combinations of ECP-P1 1 cannot appear on the basis of the definition of ECP. The intersections of columns 3–8 and lines 1–16 indicate the signals that the analyzer produces in appropriate cases (+ - a negative sign of the remainder is detected, and at the stage the divisor will be added

to it, - - a positive balance is detected, and the divisor at the current stage will be subtracted from this residue), and signs that will be set by the analysis mode block for the subsequent division stage .1

Based on the analysis of the table in

device has two modes

analysis: the mode in which the PN “, and the mode in which

POP + PU11.P1 1.

If there is no POP situation

  1, then for lines 1-6 the analyzer always generates a signal +, if POP-PUUP1 1, then the analyzer is independently of 5152, P2PZ produces a signal -.

If POP + PUP-P1 1, then the analyzer for lines 11-16 always produces a signal - and if POP + PUP 3 is a transfer from the highest bit of the remainder to the sign bit (if the specified transfer is generated at the next (addition stage, then); POP is prospective negative overflow, (if the remainder is negative), and not having information about the lower bits of the bitwise sum codes (S2, 53 ... Sn) and bitwise transfer (PZ, P4 ... Pn ), it can be assumed that the obtained residue can be modulo not less than 0.5 (i.e., after shifting it one digit to the left, get a negative number, not less than, then the analyzer independently of S1S2, P2PZ produces a signal +. To form POP and PUP, the following logic is used: PUP-. (P2 + 51) P2 $ 2 P2 51 pg .: pop. 14POP .-EPUP. POP. +.. ni,., + (non.nvn.-m ,,,) .- n, 4, (i is the number of the measure). The control unit generates at each division step, where the next the discharge of the private, the following. one after another is the control signal circuit, the first controlling signal-paraphasic I1, I1, I2, IZ, I4. In the initial state, zero is set in the operation trigger 109 and in the counter 107. The control signals I1, I1, I2, IZ, I4, respectively ... at the outputs 32, 31, 30, 29 and 28 are absent. No signal End of operation at output 27, B. Before the start of division, the control unit (input 26) receives a start signal, counter 107 sets the code of the number that determines the number of division cycles, operation trigger is set to state 1, which enables the second input element I 113, to the first input of which, after the code is installed in the counter, also receives an enable signal from the output of the first element NO 111. As a result, signals from the generator 110 pass through the first element 113 and through the HE elements 112 delay 116-119 - and care The control signals are generated at the outputs 31, 32, 30, 29, and 28. In addition, each regular signal from the output of the first delay element 116 is fed to the counting input of the counter 107, reducing its content by one. Signals from the generator of the signal generator 110 will pass; Through the first element AND 113, until a zero appears in the counter 107. As the zero value in the counter 107 turns on, it passes through the analyzer 108 zero and allows the passage of signals from the generator 110 through the second element AND 114, and the first element NOT 111 prohibits the passage of signals through the first element AND 113. The operation trigger is set to zero, and output 27 The end of the operation of the control unit appears indicating the completion of the 03 division operation. The delay element 116 is needed so that the signals at the outputs 32 and 31 are opposite in value and are formed at the same time instant. The notation in FIG. 5: TP is the output of the trigger trigger unit 109, the HS is the output of the signal generator 110, A O is the analyzer output 108 zero, the COP is the output signal 27 End of operation of the control unit. The delays between the signals I1 and I2 (the value of the delay of the element 117) are chosen so that the flip-flops 85 and 86 are reset after the appearance of the signals at the outputs 49 and 50 of the block for determining the analysis mode when forming the output signals in the analyzer. The delay of the OF signal with respect to I2 is chosen so that the reset of the flip-flops 85 and 86 of the analysis mode determination block 45 does not overlap the process of installing one of them into the unit state. The signal I4 is delayed relative to the signal I 1 in such a way that the shift of the registers 54 and 58 of the dividing device takes place after the installation of their least significant bits to one. The period of the OF signals is chosen sufficient to complete the addition operation in the adder. The device for dividing works as follows. In the initial state, the divider without the sign bits is located in the register 20 of the divider (Fig. 1) the dividend without the leading bit and the sign bits is placed in the register 11 of the bit amount. All bits of the register are 58 negative digits of the private and all bits except the penultimate lower register 54 positive digits of the private are at zero. The analyzer trigger 102 is in the single state, and the trigger 101 of the same block (Fig. 3) is in the zero state, the triggers 85 and 86 of the analysis mode determination unit (Fig. 2) and the trigger 109 of the control unit (Fig. 4) . are in the zero state. The output 36 of the analyzer 33 is present signal (Fig. 1). In bit-wise register 16, FIG. 1 is set to zero code. At the outputs of the bit-sum 4 and transfer 6 of the adder 1 (Fig. 1), there is a two-digit code of the difference shifted by a digit to the left (multiplied by two) of the dividend and the divisor i. the first remainder, the values of its high-order bits of the bit amount of 51S2 and the transfer of П2ПЗ, as well as the transfer to the sign bit P1. present at the respective outputs 8-10 of the adder 1 (FIG. 1). The division begins upon receipt of a signal. The start-up to the input 26 of the control unit 25, according to which the operation trigger 109 is installed in the unit (Fig. 4), and the control unit begins to generate for each division stroke a sequence of I1 and W, I2, IZ, I4. The division clock (or stages of division into a set of which the next digit +1 or -1 quotient is determined) is performed similarly, at the beginning of each clock cycle the signal I1 at the output 32 of the control unit is allowed to receive the same amount codes and transfer from outputs 4 and 6 of the adder 1 are correspondingly in registers of the bit sum of 13 and transfer 16 (Fig. 1). At the same time, using the signals I1 and I1, the analyzer 3 determines taking into account the signals at its inputs 44 and 35, determining the current balance, and at inputs 42 and 43, which characterize the analysis mode, form The unit of the analysis mode determines the current quotient and the type of operation (addition or subtraction) to be performed at the current dividing cycle, or does not output any output signals. In the first case, the signal on the control input 23 of the reverse code of the register 20 is provided to the second information input 5 of the adder 1 inverse of the divider code and the sending of a signal to the input 2 for transferring the least significant bit of the same accumulator 1; moreover, the signal at the input 55 of the register 54 sets the unit to its least significant bit. In the second case, the signal at input 22 transfers the second informational input 5 of the adder 1 to the forward splitter code, and the signal to the input 60 to set the unit to the digit register register 58. In the third case, the code from register 20 to the adder 1 is not transmitted, and zero values are stored in the corresponding bits of registers 54 and 58. The signal 112 clears the triggers 85 and 86 of the analysis mode determination unit 45 (FIG. 2), and the I 3 signal polls the logical goals of the same block, which form the characteristics of the analysis mode for the next division cycle. As a result, the trigger 85 (prospective negative overflow) or the trigger 86 (previously taken into account transfer) can be set to one. The signal I4, coming from the output 28 of the control block 25 to the inputs 56 and 59, respectively of registers 54 and 58, shifts the codes of these registers by one bit in the direction of the higher bits. The current clock will be completed when at outputs 4 and 6 adder 1 will be formed another two-step code residue. The last dividing cycle is performed in the same way as the previous ones, with this only difference that in control block 25 (Fig. 4), a zero value will be obtained in counter 107 during this cycle. Therefore, when a signal is generated by the generator 110, after the last the cycle is set to zero of the operation trigger 109, and a signal is generated at the output 27 of the control unit 25, which is outputted at the end 65 of the operation of the dividing device. This division operation ends. At outputs 4 and 6 of adder 1, a two-row code of the remainder will be presented, and the quotient found will be represented as two codes: codes of positive digits at output 67 and negative digits at output 66 of the division device. The transition from such code to binary in the proposed device is not considered. Such a transition can be carried out as described in the EC, or as it is done in an EC-1050 43 computer processor. For determining the quotient in a known device, an additional adder and analyzer are used, in the proposed device an analysis mode determination unit and 15 analyzers that require less equipment costs compared to lime, device. The duration of the division stroke in the proposed device is 2.3 times 1141AOZ16 less than in the known device. Thus, the proposed dividing device is very fast by reducing the hardware costs of the equipment.

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Claims (1)

DEVICE FOR DIVISION, containing an adder, a register of bitwise sum, a register of bitwise transfer, a register of a divider, a register of positive digits of private, a register of negative digits of private, a control unit and an analyzer containing an OR element, the first and second AND elements and NOT, the first and the second information inputs of the adder are connected respectively to the outputs of the bitwise register and transfer registers, and the third information input of the adder is connected to the output of the register of the divider, the information input of which is connected to a device divider input, the dividend input of which is connected to the first information input of the bitwise register, the second information input of which is connected to the bitwise output of the adder, the bit transfer output of which is connected to the information input of the bit transfer register, the low-order transfer input of the adder is connected to the control input of the reverse output the divider register code, the control input of the reception of the register code of the bitwise sum is connected to the control input of the reception of the register code of the bitwise first transfer and with the first control output of the control unit, the second control output of which is connected to the shift inputs of the registers of positive and negative digits of the quotient, the outputs of which are connected respectively to the first and second outputs of the device, the start and exit end of which are connected respectively to the start and exit input The end of the operation ”of the control unit, characterized in that, in order to improve performance, a unit for determining the analysis mode is introduced in it, which contains the first, second, third and fourth elements nts OR, first, second, third, fourth, fifth elements NOT, first, second, third, fourth, fifth, sixth, seventh, eighth elements AND, first and second triggers, and in the analysis mode definition block, the output of the first trigger is connected to the first the input of the second element OR and with the third input of the first element And, the second input of which is connected to the first input of the second element And and the output of the second trigger, the installation unit of which is connected to the output of the eighth element And, the first input SU. ,,, 1141403 which is connected to the output of the fourth OR element, the first input of which is connected to the output of the sixth AND element, the first input of which is connected to the second input of the third OR element and the output of the fifth element NOT, whose input is connected to the output of the second OR element, the installation input of the unit of the first trigger is connected to the output of the seventh AND element, the first input of which is connected to the output of the third OR element, the first input of which is connected to the output of the fifth AND element, the three inputs of which are connected respectively to the outputs of the first of the second and third elements are NOT, the input of the first element is NOT connected to the first input of the third element AND ,, ... whose input is connected to the second input of the first OR element, the output of which is connected to the fourth input of the fourth AND element, the first input of which is connected to the second input of the sixth AND element and the output of the fourth element NOT, the input of which is connected to the output of the third AND element, output the first element AND is connected to the input of the third element NOT, the outputs of the second and fourth elements AND are connected respectively to the second inputs of the second and fourth elements OR, the second inputs of the seventh and eighth elements AND are connected to the third control them . the output of the control unit, the fourth control output of which is connected to the inputs of the zero setting of the first and second triggers, the first and second inputs of the first and second elements AND are respectively connected to the transfer output to the sign digit of the adder, the analyzer additionally contains the second, third, fourth, fifth elements OR , the third, fourth elements And, the first and second triggers, moreover, in the analyzer the outputs of the triggers are connected to the control inputs of the output of the forward and reverse codes of the register of the divider, respectively, the input settings and the units of the first trigger are connected to the information input of the register of negative digits of the quotient and to the output of the element NOT, the input of which is connected to the output of the fourth element AND, the first, second, third, fourth inputs of which are connected respectively to the outputs of the first, second, third, _ fourth elements OR, input (unit settings of the second trigger are connected to the information input of the register of positive digits of the quotient and to the output of the fifth OR element, the first, second, third inputs of which are connected respectively to the outputs of the first of the second, third and third AND elements, the third input of the third AND element is connected to the output of the first OR element of the analysis mode determination unit, the output of the second OR element of which is connected to the second input of the fourth OR element, the third input of the second AND element and the fourth input of the third AND element of the analyzer, the first input of the first AND element which is connected to the third input of the third OR element, the fourth inputs of the first and second OR elements of the analyzer and with the output of the first AND element of the analysis mode determination unit, the first control The output of the control unit is connected to the zero-setting inputs of the first and second triggers, the second input of the first AND element, the fourth and fifth inputs of the second and third elements AND of the analyzer, the fifth inputs of the first and second elements OR of which are connected to the first input of the fourth OR element, the fourth input of the third the OR element, the analyzer and the fifth control output of the control unit, the first inputs of the first and second elements OR and the third element AND of the analyzer are connected to the second input of the fourth element AND of the block analysis mode and the output of the second senior transfer category of the adder, the output of the first senior transfer category of which is connected to the third input of the first OR element, the second input of the third OR element, the second input of the second analyzer element AND and the first input of the first OR element of the analysis mode determination unit, the input of the second which element is NOT connected to the third input of the second OR element, the first input of the third OR element, the first input of the second AND element of the analyzer and the output of the first senior bit of the sum a, the output of the second senior bit of the sum of which is connected to the second inputs of the first and second elements OR and the third element AND of the analyzer and the third input of the fourth element AND of the unit for determining the analysis mode, in addition, the control unit contains a signal generator, operation trigger, counter., analyzer zero, the first and second elements are NOT, the first, second and third elements AND, the first, second, third and fourth delay elements, and in the control unit, the start input of the control unit is connected to the installation input of the operation trigger unit and that a fixed counter input, the counting input of which is connected to the first output of the control unit, the input of the second delay element and the output of the first delay element, the input of which is connected to the input of the second element NOT and the output of the first AND element, the second input of which is connected to the output of the operation trigger and the first input of the second element And, the third input of which is connected to the output of the signal generator and the third input of the first element And, the first input of which is connected to the first input of the third element And and the output of the first element NOT, whose input connected to the second input of the second element And and the output of the zero analyzer, the input of which is connected to the output of the counter, the input of setting the zero of the trigger is connected to the output of the second element And and the output The end of the operation of the control unit, the second output of which is connected to the output of the third element And, the second input which is connected to the output of the fourth delay element, the input of which is connected to the fourth output of the control unit and the output of the third Delay element, the input of which is connected to the output of the second delay element and the third output a control lock, the fifth output of which is connected to the output of the first element NOT.