SU1109738A1 - Device for selecting ordered sequence of data - Google Patents

Abstract

DEVICE FOR BbfBOPA OF ORDERED DATA SEQUENCE, containing n input registers, n decoders, and result registers (groups of elements H, h groups of elements OR, the switch, the outputs of which are outputs of the device, the analysis unit, including analysis bits, each of which contains (p-1) elements AND, (g -1 j miEHTOB No. and a multi-input element OR, and the outputs of each i-th register, whose inputs are the inputs of the i-th sorted number of the device, where, 2, ... , h, n - the number of sorted numbers, connected to the inputs The i-ro of the decoder and with the information inputs of the ix elements AND each -th group, j- and the output of each -th decoder are connected to the iM input j-ro of the bit analysis node, where, 2, ..., m, m is the number of bits The numbers of the sorted numbers are sorted, in each JM by the bitwise bottom of the analysis node the kth input, where 1 1, 2, ... ..., (n-1) is NOT connected to the (k + l) th inputs through the kth element k-ro, (k + l) -th, ..., () -th elements AND, each p-th input of the bit analysis node is connected to the first input (p-1 | th-th elements, where, 3 ,. .., No., the first input of the j-ro of the bit node is connected to its first output, and the output of the kth element AND of the bit code the analysis node is connected to the (K + 1) th output of the analysis node, the element outputs of the V-th group of the device are connected to the corresponding inputs of the 1st element OR of the group, the outputs of the NG elements of the group and the group are connected to information inputs) th register of the result, the outputs of which are connected to the information inputs of the i-group and the switch group, which contains h (And groups of elements And, the decoder and gistr, the inputs of which are connected to the Array Size bus, and the outputs with the corresponding inputs of the decoder, i-and the output of which is connected to the first the inputs of the first and second elements, ..., (i and groups, the information inputs of the i group of the switch with connected to the second inputs of the elements of the I group, the polling inputs of the elements 00 00 of the AND of all groups are connected to the control input of the switch, bus Initial blanking is connected to the inputs of the installation in the O input registers and result registers, the bus Polling is connected to the control input of the switch, which is so that, in order to improve speed, signal formation nodes were introduced into the device census, and in the unit of analysis of h nodes code development, each t-fi census signal generation node contains n elements OR and

Description

n groups of elements and m elements in each group, and in each node of forming the census signals the outputs of the elements of the i-th group are connected to the inputs of the ii-ro element OR of the node forming the census signals, each j is the code conversion node, where, 3, ..., p, contains m elements AND and m elements NAND, and the output of the j-ro element NAND is not connected to the JM output of the j-th group of information outputs of the analysis block and its BTopbiM input of the j-th element AND

(j ll-ro Wela code conversion, the output of the j-ro element And the code conversion node is connected to the direct input

j-th element AND-NOT, with (j + l) -th inverse inputs of the (j + l) -th, (, th-th element AND-NOT and with the first input j-ro element AND (j + l) -th node of the code conversion, the first code conversion node contains m AND-NOT elements, moreover, the output of the j-ro element H-NOT is connected to the JM output of the first group of information outputs of the analysis unit and with the second output j-ro

element And the second node conversion codes, the output of the logical sum

The j-th bit-by-bit analysis node is connected to the direct input of the j-ro element AND –NE, with (j + l) -th inputs (j + 1) -th, (j + 2) -th, ..., hi- elements of the NAND of the first code conversion node,

The i-th output of the j-ro bitwise analysis node is connected to the i-th input of the multi-input element SHS, the output of which is the output of the logical j-ro bit of the bitwise analysis node, the i-th output of the j-ro bitwise analysis node the analysis unit is connected to the control inputs of the j-ro element AND th group of each i-ro node for generating census signals, the information inputs of JX elements AND of all groups of the 4th node for generating census signals are connected with the output of the j-ro element AND-NOT i -ro node for the conversion of the analysis block codes, output of the i-ro element Ш1И of the i-ro node of signal generation s census connected with the control inputs of all AND elements (ii) -th group of devices.

The invention relates to automation and computing and can be used in the implementation of data processing systems and automated control systems.

A device for determining the least of the numbers is known, containing input registers, decoders, bit-wise analysis nodes, performed on the elements NOT and AND, elements OR 1 J.

The disadvantage of this device is low speed in the formation of an ordered sequence of data, since for the formation of an ordered sequence of numbers, n cycles are required, in each of which the analysis and selection of the smallest number is performed.

The closest to the technical essence of the invention is a device for selecting an ordered sequence of data containing input registers, decoders, result registers, block

control, switch, groups of OR and AND elements, element OR, groups of input elements AND and OR, bus Start operation, Initial blanking and Array size, analysis unit consisting of OR elements and individual analysis nodes, with outputs of each i -ro register, where i 1,2, ..., h, are connected to the inputs,

 -th decoder and with informational inputs of elements AND of the i-th group, and outputs of the i-th element OR are connected to the control inputs of the elements AND 1st group, the outputs of the elements AND

of each i-th group are connected to the inputs of the 1SHI group elements, the outputs of which are connected to the inputs of the result register, each output of the i-ro decoder is connected to

t-M input j-ro bit unit of analysis, where j-l, 2 ..., m, m is the number of bits of the sorted numbers, each .i-th output j-ro of the bit-specific node analysis connected to the j-th input of the

of the OR element, and the output of each k-th bitwise node a.anza, where, 2, ... Dgp-1), is connected by the control input to the + 1) -th serial node of the analysis, each j-th digit node analysis consists of elements AND, n elements NOT and a multi-input element AND, each 1-and the input of the bit analysis node is connected to the first input of the i-element And, the control input of the bit analysis node is connected to the second inputs of the elements AND input of the k-th bit of the analysis node is connected to the i-th element NOT to the (i + 2) -th move (i + l), li + 2), ..., h -th element input element I, the output of which is connected to the output of the transfers of the first bit analysis node; the output of each i-element of the AND is connected to the output of the digital block of the analysis, ni, and the direct analysis node consists of the elements AND (nl) -th element is NOT, each pth input of the node, where, ..., (hI), is connected to the first input of the pth element AND, the input transfer of the bit of the analysis node is connected to the second inputs of the elements And, every pth input node of a parity analysis node through the pth element is NOT connected to the (p + 2) th input (p + G), (p + 2) ,, .., pth elements AND , yyyy entrance No.- about the bit analysis node is connected to the (t - "- 2) th input of the nth element AND, the output of each i-ro element I is connected to the 1st output of the ni-th bit random analysis node, the output of the analysis unit connected to the output of the i-ro element OR of the analysis block is connected to the first control inputs of the 1 elements AND in each of the H groups of elements | 01И, where 1,., ..., r ", whose information inputs are connected to the outputs E- first input register, and, to the first input of the i-th element AND group of input elements And, the second inputs of all elements of the group of input elements And connected to the output of the el OR, the output of the i-th element of the group of input elements AND with the first input of the i-ro element of the group of input elements OR whose output is connected to the input of the i-ro input register, the th output of the control unit is connected to the second control inputs of all elements of the I – n group and to the t-th input of the element YS, the outputs of the elements I “and groups from (8p) groups are connected to the corresponding inputs of the i-ro element HIIH (-OUT group whose outputs

connected to the information inputs of the i-th result register, the group of information outputs of the i-ro register, the result is connected to the corresponding information inputs of the J-group and the switch, whose outputs are the information outputs of the device, the control input of the switch is connected to the output of the control unit, the initial bus blanking is connected to the installation input of the control unit, with zero inputs of the output registers and with the second inputs of all elements of the group of input elements OR, bus The size of the array is connected to the information the inputs of the switch and control unit, which contains the control trigger, the counter, the decoder, the AND, OR elements, the group of elements AND, the pulse generator whose output is connected to the first input of the AND element, the second input of which is connected to the direct output of the control trigger and the first inputs5 And the group of elements, and the output with the counting input of the counter, informational outputs of which are connected to the decoder, the i-and the output of which is connected to the second input of the i-th element of the group, the output of which is the iM output of the control block, the output signal the overflow of the counter is connected to the first input of the OR element, the second input of which is connected to the bus. Initial damping, and the output

5 of the OR element is connected to the zero input of the control trigger, the single input of which is connected to the input

the control unit settings, and the inverse output is the control output of the control unit, the information inputs of the control unit are connected to the installation inputs of the counter, the switchboard contains groups of elements AND, the decoder, the register whose inputs are connected to the inputs of the switch, and the outputs are with the corresponding the inputs of the decoder, the i-th output of which is connected to the first inputs of 1,2, ..., -x groups of elements AND, the information inputs of the i-th group of the switch are connected to the second inputs of the elements I of the i-th group, the control inputs of the elements AND all g The control panel is connected to the control input of switch 2 ..

 The disadvantage of the device. is a low speed in the formation of an ordered output array, since to obtain it requires an appropriate number of cycles

devices. The cycle time is determined by the logical depth of the circuit. we are choosing an extreme number. With an increase in the size of the output array, the total time spent on obtaining an ordered data sequence increases.

The aim of the invention is to improve the speed of the device.

The goal is achieved in that a device for selecting an ordered data sequence containing input registers, decoders, n result registers, (nnl groups of AND elements, n groups of OR elements, a switch whose outputs are device outputs, an analysis unit, including parity analysis nodes, each of which contains (n-1) AND elements (yy-1 1 NOT elements and a multiple-input OR element, and the outputs of each i-th register whose inputs are the inputs i-ro of the device number to be sorted, where 1,2, ..., p .h is a number of the sorted numbers., connect with the inputs of the i-ro decoder and with the information inputs of the ix elements of the TOO AND of each i-group, the i-th output of each 1 g of the decoder is connected to the H input of the j-ro bit unit of analysis, where, 2,.,., t, t is the number: the bits of the sorted numbers, in each JM by the bit of the analysis node is the k-th input, where is 1,2, ..., (n-1) through the k-th element E is connected to () th inputs, Ik + l, ..., (l -1) -th element AND, each p-th input of the bit analysis node is connected to the first input of (p-1) -th element AND where, 3, ..., h, the first input of the bit analysis node is connected to its first one go, and the output of the k-th element of the bit analysis node is connected to the (K + 1) -th output of the bit analysis node, the outputs of the elements of the i-th device group are connected to the corresponding inputs of the i-ro element OR of the i-th group, . the outputs of the elements of the lane of the i-th group are connected to the information inputs of the i-th register of the result, the outputs of which are connected to the information inputs of the i-th group of the switch, which contains n groups of elements I, the decoder and the register, the inputs of which are connected to the bus Array size, and the outputs with the corresponding inputs of the decoder, the i-th output of which is connected to the first inputs of elements AND of the first, second, ..., i-th groups, the information inputs of the i-group and the switch group are connected to the second inputs of elements AND 1 of the group, the polling inputs of elements V and all groups cone Ina with the control input of the switch, bus Initial blanking is connected to the installation inputs in the O input registers and result registers, the bus Poll is connected to the control input of the switch, n scoring census signaling nodes are entered, and i, each i. -and the census signal generation node contains n elements of the W and H groups of elements AND by TTL elements in each group, with each node forming the census signals output elements AND the i-th group are connected by f inputs of the i-th element OR form node world census signals, each J-th code conversion node, where, 3, ..., h, contains m elements AND and gp elements AND-NOT, with the output of the j-ro element AND-ЫЕ connected to the JM output of the j-th information outputs of the analysis unit and its second input of the j-ro element of the AND (j + l) -th conversion node, the codes, the output of the j-ro element AND of the node -Conversion of codes connected to the direct input of the j-ro element -IND,

with (j + I) -MH inverse inputs () - th, (j + 2) -th, ... of the m-th AND-NOT element. with the first input of the j-ro element I (j +1} of the code conversion node, the first node of the code conversion contains n I-NOT elements, with the j-ro input of the I-N element connected to the iM output of the first group of information outputs of the analysis unit and with the second input of the j-ro element AND the second node of the code conversion, the output of the logical sum j-ro of the bitwise analysis node is connected to the direct input of the j-ro element NAND, with ("1) -th inputs j-fl) - go, (} n-2) -th, ..., t-th element AND-NOT of the first code conversion node, ij-th output J-TO of the bit analysis node connected to the I-MU input of a lot input element OR, the code of which is the output of the logical sum of the i-th bit of the analysis node, the i and output of the j-ro of the analysis node of the analysis block is connected to the control inputs of the j-ro element AND the j-th group of every 1st census signal generation node, information inputs of jX elements AND all groups

The i-th census signal generation node is connected to the output of the j-ro element of the NAND of the i-th code conversion unit; the output of the i-th element OR the i-ro node of the census signal generation is connected to the control inputs of all elements AND (ii) -and device groups.

FIG. 1 shows a block diagram of the device; in fig. 2 - block diagram of the analysis unit; in fig. 3 is a block diagram of a bit analysis node; in fig. 4 is a schematic diagram of a census signal shaping node; in fig. 5 - switch block diagram.

The device of FIG. I) contains information input buses J ,, - 1, connected to the inputs of the corresponding input registers 2 ,, connected to the inputs of the corresponding decoders 3j, output buses i, which are connected to the analysis unit 5, groups of information outputs 6 and group of control outputs 7 of which connected to the control units 8, the output buses 9, ..., 9 9 of which are connected to the control inputs of the element groups and 10, - 10 ,, ..., 10. whose outputs are connected to the corresponding OR OR I elements of the groups, the outputs of which are connected to the corresponding information inputs Result registers 12, Outputs 13 and 13 registers are connected to a switch 1A, whose output buses are informational outputs of the device, bus 16 Initial blanking, bus 17 Array rails and bus 18 Poll.

The analysis block (Fig. 2) contains the bitwise I9 -, - 19 analysis nodes, the 20. 20. 20 conversion codes, the AND-NOT element. 21 and element 22.-node code conversion.

The bit analysis node (Fig. 3) contains the HE elements 23,. multi-input element OR 24 and elements AND 25.

. The census signal generation unit (Fig. 4) contains groups of elements And 26, - 26,., .. r elements in each and n elements

OR 27 - 27..

The switch (Fig. 5) contains a register 28 connected to the decoder 29, the output signals of which are connected to the elements And 30f |.

The device works as follows.

The formation of an ordered sequence of numbers from the original ones is based on the transformations of q washing of the decoders of binary codes of numbers to distribution codes, and then comparing the like outputs of the decoders.

 Let there be four numbers a 101.aj-l10 ,, ,, located in the respective registers. It is required to transform this sequence into ordered descending numbers. These numbers are converted by decoders, the output signals of which are not shown in Table. one.

In tab. 1 Q, - OT - signals of the logical sum, and .- signals of the analysis circuits.

Table

and 010О 100 00 О q

QI .. 7

From tab. 1 it follows that the smallest number is in the third register, the next number in the fourth, then in the first, and finally in the second. Thus, the ordered sequence of numbers is as follows: aj, a, a, a,

From here, in the first output register of the result should be placed. the number in the third input, in the second - the number from the fourth input register, in the third - from the second and in the fourth - from the first input register.

The indication of what is the first smallest number is the extreme left of the commander in the table. one.

For this example, this is the signal Q-, further -Q2. Information about the number of the input register where the extreme number is located is contained in the index of the signal o, (respectively

.. - t -I. , ..HI1CH4 CH1CHG2Gak1 1 way, if the code of Q Qy signals is transformed so that it has a single unit that determines the volume of the random analysis node, then with the signals |, -c (of this node you can transfer the smallest number to the corresponding result register .

So, for the first output register, the binary code 1100110 is converted to code 1000000, and for the second output register from code 0100110 to code 0100110, / Next, for the third output register from code 0000110 to code 0000100 and for the fourth, code 0000010.

The code conversions for the output registers are using the code conversion nodes of the analysis block 5 (Fig. 2I) as follows.

Preliminarily, output signals are formed by bit analysis nodes (Fig. 3) - by means of the elements AND signals, by means of the element OR 24. Analysis unit 5 (Fig. 2) contains AND conversion units. In the first transform node, consisting of -from m I-IE elements, is formed at the outputs 6-6 | binary code of logical-sum Q signals.

The signal of the logical sum from the output 19 closes all elements of N-NOT 2C in the first inverse inputs. Thus, on the information ones. In the outputs of the first group, a binary inverse code 0111111 is formed. The same signals and the corresponding signals Q., - Q-, act on the inputs of the And 22 elements of the second transform node. At the outputs of the And, 2 elements, a binary direct code 0100110 is formed.

Thus, the transformation nodes form codes in which the position number where the signal has a zero value corresponds to the number of the bit analysis node 19 determining the value of the next extreme number.

Binary codes are formed in four transformation nodes: 0111111, 1011111, 1111011, 1111101. This means that the information on the size space, minimum number for the first output register I2 (Fig. 1) is in the first bit-sized node 19 of the analysis I) of the IG. 2), for the second - in the second node (192), D - the third - in

Vol. U9;) AND FOR the hardened output register in the sixth bit bit node 19 (j analysis.

These signals as the OHH6IX information are sent to the corresponding nodes 8j, controls, which are based on the control signals - "v (tab. They allow the formation of a control signal at output 9.) of the node 8, for example for the first register. On this signal, the number from register 2 is transferred to the output register

42 ,.

Similarly, the transfer of numbers from the remaining input registers 2 to the weekend 122-2 is provided.

Thus, by converting the binary code of the logical sum signals of the bit analysis nodes, the location of the numbers is determined to obtain an ordered array and the control signals are generated on this basis to realize the initial ones. numbers in result registers.

Using the switch 14, a Polling signal is sent via bus 18 to provide the specified size of the output array to the information outputs 15 of the device.

Let it be necessary to output two numbers from the array of four numbers to the output of the device. The code of this number goes to register 28 (Fig. 5).

The pefHCTpa size is determined by the maximum size of the initial array of numbers h and is chosen by the expression: /.

- /

In the interpreter 29 will be excited the second output, allowing the operation of the elements And 30 and 30 liters. According to the Polling signal received via bus 18, the output signals of the registers 12, 12 through the buses 13, 132 through the elements And 30 and 30 are sent to the output buses 13, 132 of the device.

Using the proposed device, it is possible to form an ordered increasing sequence of numbers. In this case, the initial numbers in registers 2 - 2 are taken in the reverse code. The output sequence will also be in the reverse code.

The device works as follows.

First, the bus 16 Initial blanking receives a signal by which the input registers 2 and output 11I registers 2 are set to zero states. Then, iio's input buses 1, -1 are assigned to registers 2 original numbers. If you need to get a descending sequence, then the numbers come in the direct code, ec; n1 increasing - inversely. At the same time, on the bus 17 Array size in register 28 is received the binary code of the required array. . Subsequently, binary codes are generated at each conversion node code (FIG. 2) so that the number position of the zero value of the signal determines the number of the bit analysis node 19, whose output signals are used to transfer the extreme number from the corresponding input register 2 to the output Register 12. Formation of output signals in. Registers 12 are determined by the delay time in the formation of information signals. Therefore, the Poll signal on bus 18 arrives at the end of the transfer of numbers to the output registers. The size of the generated sequence is determined by the binary code and the size of the array, according to which a machine is excited in ds1lifrater 29 (Fig. 5), the number of which corresponds to the size of the specified output array. In accordance with this output, the specified output array is set at the outputs of the device 15. and the principles of operation of the known device, the time of formation of the output ordered data sequence is determined by the sequence of pulses of the generator of the control unit and the size th output pulse repetition array hara ized time period of one cycle of operation of the device depends on the delayed time; when choosing an extreme number. To form an array of size / in numbers (part 1, the operation time of the devices is T tj, t |., Where the pulse repetition period of the control unit. The minimum pulse repetition period is equal to f, are the delayed-ek times in the OR, AND elements, and input register triggers, respectively; RDc is the time of operation of the decryption device, which can be taken equal to ANES (analysis parity by the analysis unit, the maximum delay time of which is determined the last 1 m (m-th) bit analysis node. ... If we accept that. ,, 2% -t33, then VltV M u HV PZ. In the proposed device, the selection time of a given array is determined from the time of supply / source numbers to the input registers until the signal is sent Polling. This time is determined by the delay time in the device and is defined as.: T H H HE u J.-He and -NOT / time of the analysis unit; - delay time in the NAND element; hp-not delay time in the control unit. If you accept that t.ng is 2Г + T, then .c.2T.T., ( V, .2in} xj (ni): 4c; n + u; . (i) The gain in speed is determined by the expression T ..- T,, (3) Substituting in the expression (3 (expressions (1) and (2), we get 17air- (4rn-i: 12f) W L ... 100% .lZili ± 12), oo, moreover, C | 4.h. Let us determine at what ratios of quantities (and h it is ensured gains in speed. Obviously, the gain in fast-action will always be when V ((. 0 Hence, transform the expression (4), GET .. iZ5..ll2):.,. I.e. 17c, - (4p + 12) 0. .or or 4h + 2 T and I, From the expression (5) you can see that the gain in speed is ensured for h with l 2, Determine in what condition, and n, the speed is reached in speed. l n "2, then from expression (5) it follows that 8 + 12 20 17 17, that is, with n 2, q, must be equal to 2 If n 3, then 24 I, -77-, i.e., 3. From the above calculations it follows that the gain in speed is achieved at A7 2 for any values, with t, n. For the case when an, table 2 shows the values of W for various values of Table2 16 32 64 4 58 67 72 From Table 2 shows that the transformation of large data arrays using the proposed device is more preferable than the known one. This highest performance gain is achieved by obtaining an output ordered array of the same size as the original,

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Claims (1)

A DEVICE FOR SELECTING AN ORDERED SEQUENCE IS GIVEN THEM, containing η input registers, and decoders, l result registers, (pl | groups of elements AND, l groups of elements OR, a switch whose outputs are the outputs of the device, an analysis unit that includes bitwise analysis nodes, each of which contains (η-l Elements Й, (l -1) elements NOT and a multi-input OR element, and the outputs of each ί-th register, the inputs of which are the inputs of the i-th sorted number of the device, where ί = 1,2, ... , η, l - the number of sortable numbers, connected to the inputs of the i-th decoder and with the information inputs of the i-th elements And of each ί-th group, the j-th output of each i-ro decoder is connected to the ί-th input of the j-th bit analysis node, where j = l, 2, .. ., m, m is the number of bits of the sorted numbers, in each j-th bit of the analysis node the k-th input, where 1 = 1,2, ... .., (η -1) through the k-th element is NOT connected to the (k + 1) -th inputs of the k-th, (k + 1) -th ,. .., (nl) -ro elements And, each p-th input of the bitwise analysis bridle is connected to the first input (p-1 | -th element And, where p = 2,3, ..., L ', the first input j -ro of the bit-wise analysis node is connected to its first output, and the output of the k-th element AND of the bit-wise analysis node is connected to (1 + I1-th output of the bit-wise analysis node, the outputs of the elements And the 1st corpse of the device are connected to the corresponding inputs | - of the OR element of the ί-th group, the outputs of the elements of the OR of the I-th group are connected to the information inputs of the j-th result register, the outputs of which are connected to the information inputs mi ί —th group of the switch, which contains l groups of AND elements, a decoder and a register whose inputs are connected to the array size bus, and the outputs - with the corresponding inputs of the decoder, the ith output of which is connected to the first inputs of the AND elements , ..., ί-th group, the information inputs of the switch group are connected to the second inputs of the AND elements and the} -th group, the polling inputs of the And elements of all groups are connected to the control input of the switch, the bus blanking is connected to the installation inputs to 0 input registers and registers result tire And the Poll is connected to the control input of the switch, and so on, in order to improve performance, l census signal generation nodes are introduced into the device, and each i-th node in the analysis unit is l code conversion nodes the census signal generation contains η OR elements and> P groups of AND elements with m elements in each group, and in each node of the census signal generation, the outputs of the And elements of the i-th group are connected to the inputs of the i-ro element OR of the census signal generation node, each j-th code conversion node, where j = 2 , 3, ..., n, contains m AND elements and tn AND-NOT elements, and the j-ro output of the AND-NOT element is connected to the jth output of the j-th group of information outputs of the analysis unit and its second input j-ro of the element ((j +1) th node of the code conversion, the output of the j-ro of the element AND of the node of the code conversion is connected to the direct input of the j-ro of the element AND -NOTE, with the (j + Ι) th inverse inputs of the (j + 1) th, (j + 2) th, th-th elements AND-NOT and with the first input of the j-ro element AND (j + Ι) -th node of the code conversion, the first node of the code conversion contains n-AND-NOT elements, the output of the j-ro AND-NOT element being connected to the j-th output of the first group of information outputs of the analysis unit and to the second output of the j-ro AND element of the second node code conversion, the output of the logical sum of the jth bit of the analysis node is connected to the direct input of the j-th element AND-NOT, with the (j + 1) -th inputs of the (j +1) -th, (j +2) -th ,. .., itt-ro elements AND NOT the first node of the code conversion, ί the j-th output of the bit-wise analysis node is connected to the i-th input of the multi-input OR element, the output of which is the output of the logical su-: we j-ro the bit-wise analysis node, the ίth output of the j-ro bit-wise analysis node of the analysis unit is connected to the control the inputs of the j-th element AND of the i-th group of each j-ro node of the census signal generation, the information inputs of the jx elements of all the groups of the 1st node of the census signal generation are connected, with the output of the j -ro element AND — NOT of the –th unit of code conversion of the analysis unit, the output of the ίth element OR i-ro node is formed I census signals connected to the control inputs of all AND elements (ΐϊ) th group of other components.