EP1461866B1 - Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter - Google Patents
Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter Download PDFInfo
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- EP1461866B1 EP1461866B1 EP02790575A EP02790575A EP1461866B1 EP 1461866 B1 EP1461866 B1 EP 1461866B1 EP 02790575 A EP02790575 A EP 02790575A EP 02790575 A EP02790575 A EP 02790575A EP 1461866 B1 EP1461866 B1 EP 1461866B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03M7/165—Conversion to or from thermometric code
Definitions
- the invention relates to an analog-to-digital converter according to the preamble of Claim 1.
- the invention further relates to a method of generating a logic circuit according to Claim 3.
- Said analog-to-digital converter is known from US patent No. 4,733,220.
- a similar analog-to-digital converter is known from US patent No. 5,633,636.
- a reference unit generates a measuring signal such as, for example, a thermometer signal which comprises a bit word from said first set.
- This first set is a measuring signal code. It holds for the bit words from the first set that a first part of the bit word consists of a sequence of zeros and that a second part consists of a sequence of ones.
- a first logic circuit can generate an intermediate signal which consists of a bit word from the second set.
- This second set of bit words is an intermediate code known by the name of Gray code, and the intermediate signal based on this is the Gray signal. It holds for the Gray code that the bit words belonging to successive unique values differ from one another by only one bit. This achieves that a possible defect that may arise when the measuring signal is converted into the Gray signal, for example due to the undesired change of a bit value of the measuring signal, can amount to one unit of the unique value at the most.
- the Gray signal is finally converted into the digital binary output signal by the second logic circuit.
- a disadvantage of the known analog-to-digital converter is that the first logic circuit has a relatively large logic depth (the logic depth being related to the maximum number of series-arranged processing elements in the circuit). In this respect it particularly holds that the logic depth for generating the least significant bit of the Gray code is considerably larger than the logic depth for generating the most significant bit of the Gray code. A consequence of this is that the most significant bit arrives at an output of the first logic circuit earlier than the least significant bit. In this way the conversion from the measuring signal code to the Gray code is limited by the waiting time for the least significant bit. This represents a limitation of the processing speed of the known analog-to-digital converter.
- the analog-to-digital converter according to the invention is for this purpose characterized by the characterizing part of Claim 1.
- an intermediate code hereinafter to be referred to as S code
- S signal The intermediate signal based on the S code will be referred to as S signal hereinafter.
- S codes are possible for the analog-to-digital converter according to the invention. These codes can be generated by the method according to the invention, as will be discussed in more detail below.
- the logic depth of the first logic circuit of the analog-to-digital converter according to the invention is smaller than the logic depth of the first logic circuit of the known analog-to-digital converter. The result of this is that the intermediate signal in the analog-to-digital converter according to the invention can be delivered at the outputs more rapidly than is the case with the known analog-to-digital converter. Furthermore, it holds that the logic depth of the second logic circuit (for converting the S signal into the binary output signal) of the analog-to-digital converter according to the invention is not larger than the logic depth of the second logic circuit (for converting the Gray signal into the binary output signal) for the known analog-to-digital converter. This means that the speed gain of the first logic circuit according to the invention results in a faster analog-to-digital converter. As a result, the analog-to-digital converter according to the invention can sample input signals with a higher frequency than the known analog-to-digital converter.
- the first logic circuit will comprise a number of sub-circuits, each sub-circuit generating one bit of the bit word of the intermediate signal. Since the respective numbers of bit variations in the respective columns of the matrix are at least substantially equal, the sub-circuits will at least substantially have the same logic depth.
- a preferred embodiment of the analog-to-digital converter according to the invention is characterized in that the digital binary output signal contains n bits, where n > 1 and where the number of bit changes in each column of said matrix is at least substantially equal to 2 n n .
- the logic depth of the first logic circuit in this preferred embodiment is approximately equal to n - ln n ln 2 . In this respect it is observed that the logic depth of a first logic circuit for converting the measuring signal into the Gray signal is n-1.
- the consecutive rows of the selected matrix contain consecutive bit words of the S code.
- the S code thus found may be used for realizing an analog-to-digital converter according to the invention.
- the number of bit variations is then at least substantially evenly spread over the columns of the matrix.
- the associated sub-circuits will all have substantially the same logic depth for the generation of the bits.
- a computer is utilized to traverse all the nodes via said connections made and to select at least one matrix whose respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.
- Fig. 1 shows an analog-to-digital converter 2 for converting an analog input signal 4 into a digital binary output signal 6.
- the analog-to-digital converter 2 comprises a reference unit 8 for generating a measuring signal 10 based on a comparison of the input signal 4 with a reference voltage 12.
- the measuring signal is a bit word from a first set of bit words. This first set is also referred to as a measuring signal code.
- a highly suitable type of measuring signal is a so-termed thermometer signal.
- the analog-to-digital converter 2 comprises a first logic circuit 14 which is connected to the reference unit 8 for generating an intermediate signal 16 based on the measuring signal 10.
- the intermediate signal 16 is a bit word from a second set of bit words. This second set of bit words is called the intermediate code.
- Each bit word from the intermediate code represents a unique value, with two bit words belonging to successive unique values differing by only a single bit.
- the intermediate code mentioned above may be an S code, as will be further explained hereinafter.
- the analog-to-digital converter 2 further comprises a second logic circuit 18 which is connected to the first logic circuit 14 for generating the digital binary output signal 6 based on the intermediate signal 16.
- the binary output signal 6 comprises a bit word from a third set of bit words. This third set is often a binary code.
- the Table in Fig. 2 comprises a matrix and gives a survey of a possible relationship between the aforesaid codes.
- the Table shows a possible relationship between a measuring signal code, Gray code, and a binary code for a state of the art analog-to-digital converter.
- the table further shows a possible relationship between the measuring signal code, S code, and the binary code for an analog-to-digital converter 2 according to the invention.
- the intermediate code (S code) consists of four bits. Alternatively it is possible for the intermediate code to have more than four bits so as to achieve a certain redundancy.
- the first main column “Measuring Signal Code” of the Table shows the bit words of the measuring signal code. Each bit word of the measuring signal code is built up from the bits T 15 to T i .
- the second main column “Gray Code” of the Table shows the Gray code.
- the Gray code comprises bit words comprising 4 bits G 1 to G 4 each.
- the Gray code is frequently used as an intermediate code in known analog-to-digital converters.
- the third main column “S Code” of the Table shows an S code which may be used as an intermediate code in an analog-to-digital converter according to the invention.
- the fourth main column “Binary Code” in the Table shows the binary code. This binary code is used for reproducing the digital binary output signal 6.
- the fifth main column in the Table (“Unique Values ") shows by what path (via rows of the table) a unique value is coupled to each bit word of each code.
- the analog input signal 4 is compared with the reference voltage 12.
- the reference unit 8 comprises a number of comparators (not shown in the drawing) in a manner known per se, each comparator having a first and a second input terminal. Each of the first input terminals is connected to the analog input signal 4. A unique voltage which is derived from said reference voltage is supplied to each of the second input terminals. Since the unique voltage is different for each comparator, it is possible to measure the analog input signal 4 with the various comparators and to generate a digital measuring signal 10 based on the comparisons. In this process, each comparator drives one bit of the measuring signal code in principle. With an increasing analog input signal 4, the measuring signal 10 will contain an increasing number of ones.
- the successive bit words of the measuring signal 10 in the Table of Fig. 2 show that the bit words of the measuring signal 4 can be compressed further. This is effected by a transformation from the thermometer signal 10 to a 4-bit intermediate signal.
- the 4-bit intermediate signal is an S signal (according to the state of the art, for example, a Gray signal).
- the transformation is performed by the first logic circuit 14.
- Fig. 3 shows on the left hand side by what paths the 15 bits T 1 to T 15 of the bit words of the measuring signal (see also the table in Fig. 2) are applied to the inputs of the first logic circuit.
- the first logic circuit comprises digital AND gates 20.1 to 20.11 known per se, each gate having two inputs and one output. Each of the AND gates 20.1 to 20.7 further has one input to which an inverter (negation element) is connected.
- the inverters are schematically shown in circles.
- the AND gates 20.2 to 20.8 and 20.11 have an inverter at the output.
- Fig. 3 together with the Table of Fig. 2 show that the bits G 1 to G 4 of the Gray code are delivered at the outputs of the first logic circuit 14A. G 1 is then the most significant bit of the Gray code and G 4 the least significant bit of the Gray code.
- the first logic circuit 14A comprises four sub-circuits, each sub-circuit generating a bit of the Gray code.
- This first sub-circuit for generating G 1 has a logic depth 0. This logic depth is determined by the maximum number of ports or processing elements connected in series.
- the second sub-circuit for generating G 2 has a logic depth 1
- the third sub-circuit for generating G 3 has a logic depth 2
- the fourth sub-circuit for generating G 4 has a logic depth 3.
- the first logic circuit 14B comprises digital AND gates 22.1 to 22.12 known per se, each gate having two inputs and one output. Each of the AND gates 22.1 to 22.8 further has one input to which an inverter (negation element) is connected. Furthermore, each AND gate includes an inverter at the output.
- the inverters are schematically shown in circles.
- the structure of the first logic circuit 14B is such that this circuit comprises four respective sub-circuits for generating the four respective bits of the S signal.
- the logic depths of the various sub-circuits are equal in this example.
- the reason for the equal distribution of the logic depths over the sub-circuits can be traced back in the Table of Fig. 2.
- the number of bit changes per column is approximately equal to 2 n /n.
- the bits of the intermediate signal are delivered substantially simultaneously at the outputs of the first logic circuit 14B.
- a further consequence is the small logic depth of the first logic circuit 14B, so that the intermediate signal 16 is available at the outputs of the first logic circuit 14B.
- the analog-to-digital converter according to the invention has a high data processing rate and can thus sample input signals at a high frequency.
- each bit of the bit word of the measuring signal is applied to one and only one input port of the first logic circuits.
- This measure prevents situations that may lead to unnecessary erroneous conversions.
- An example of such a situation is when a bit is applied to two different ports and when, as a consequence of the changing of the bit value of the bit, different bit words are applied to the ports.
- Figs. 5 and 6 illustrate a method of generating an S code.
- An S code may be used, for example, in an analog-to-digital converter according to the invention.
- an S code When an S code is generated, first of all a set of bit words is defined, each bit word comprising n bits (n>1).
- Every node of the diagram is connected to four adjacent nodes (boxes), so that the binary representations of the associated bit words differ by only 1 bit (see also the Table in Fig. 2).
- Fig. 5 shows, for example, that the node in which the unique 0 value occurs is connected to the nodes in which the unique values 4, 8, 1 and 2 occur (the diagram is cyclically repeated, see the dotted lines).
- a computer may be used to traverse all the nodes by every possible path via said connections provided and to select at least one matrix whose respective numbers of bit variations in the respective columns are at least substantially equal.
- the invention was described above with reference to a number of embodiments in which the intermediate code comprises four bits. However, the invention may be applied in a comparable manner to intermediate codes comprising bit words of more than four bits.
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Abstract
Description
- The invention relates to an analog-to-digital converter according to the preamble of
Claim 1. - The invention further relates to a method of generating a logic circuit according to
Claim 3. - Said analog-to-digital converter is known from US patent No. 4,733,220. A similar analog-to-digital converter is known from US patent No. 5,633,636. In the known analog-to-digital converters, a reference unit generates a measuring signal such as, for example, a thermometer signal which comprises a bit word from said first set. This first set is a measuring signal code. It holds for the bit words from the first set that a first part of the bit word consists of a sequence of zeros and that a second part consists of a sequence of ones. Based on the measuring signal a first logic circuit can generate an intermediate signal which consists of a bit word from the second set. This second set of bit words is an intermediate code known by the name of Gray code, and the intermediate signal based on this is the Gray signal. It holds for the Gray code that the bit words belonging to successive unique values differ from one another by only one bit. This achieves that a possible defect that may arise when the measuring signal is converted into the Gray signal, for example due to the undesired change of a bit value of the measuring signal, can amount to one unit of the unique value at the most. The Gray signal is finally converted into the digital binary output signal by the second logic circuit.
- A disadvantage of the known analog-to-digital converter is that the first logic circuit has a relatively large logic depth (the logic depth being related to the maximum number of series-arranged processing elements in the circuit). In this respect it particularly holds that the logic depth for generating the least significant bit of the Gray code is considerably larger than the logic depth for generating the most significant bit of the Gray code. A consequence of this is that the most significant bit arrives at an output of the first logic circuit earlier than the least significant bit. In this way the conversion from the measuring signal code to the Gray code is limited by the waiting time for the least significant bit. This represents a limitation of the processing speed of the known analog-to-digital converter.
- It is an object of the invention to provide an analog-to-digital converter that eliminates the aforesaid disadvantage. The analog-to-digital converter according to the invention is for this purpose characterized by the characterizing part of
Claim 1. For this purpose, an intermediate code, hereinafter to be referred to as S code, is used in the analog-to-digital converter according to the invention. The intermediate signal based on the S code will be referred to as S signal hereinafter. Various S codes are possible for the analog-to-digital converter according to the invention. These codes can be generated by the method according to the invention, as will be discussed in more detail below. - The logic depth of the first logic circuit of the analog-to-digital converter according to the invention is smaller than the logic depth of the first logic circuit of the known analog-to-digital converter. The result of this is that the intermediate signal in the analog-to-digital converter according to the invention can be delivered at the outputs more rapidly than is the case with the known analog-to-digital converter. Furthermore, it holds that the logic depth of the second logic circuit (for converting the S signal into the binary output signal) of the analog-to-digital converter according to the invention is not larger than the logic depth of the second logic circuit (for converting the Gray signal into the binary output signal) for the known analog-to-digital converter. This means that the speed gain of the first logic circuit according to the invention results in a faster analog-to-digital converter. As a result, the analog-to-digital converter according to the invention can sample input signals with a higher frequency than the known analog-to-digital converter.
- In many cases the first logic circuit will comprise a number of sub-circuits, each sub-circuit generating one bit of the bit word of the intermediate signal. Since the respective numbers of bit variations in the respective columns of the matrix are at least substantially equal, the sub-circuits will at least substantially have the same logic depth.
- A preferred embodiment of the analog-to-digital converter according to the invention is characterized in that the digital binary output signal contains n bits, where n > 1 and where the number of bit changes in each column of said matrix is at least substantially equal to
- The code generation method according to the invention is characterized in that the method also comprises the following steps:
- making inter-node connections such that connections are only made between nodes of which the associated bit words differ by only one bit;
- successively passing through nodes by various paths via the connections thus made, a matrix being drafted for each path, the bit words of the successive nodes being accommodated in the matrix in consecutive rows;
- selecting a matrix from the matrices thus drafted whose respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.
- The consecutive rows of the selected matrix contain consecutive bit words of the S code. The S code thus found may be used for realizing an analog-to-digital converter according to the invention. As has already been observed hereinbefore, the number of bit variations is then at least substantially evenly spread over the columns of the matrix. As a result, the associated sub-circuits will all have substantially the same logic depth for the generation of the bits.
- It preferably holds that in said method a computer is utilized to traverse all the nodes via said connections made and to select at least one matrix whose respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.
- The invention will now be further discussed with reference to the drawing in which:
- Fig. 1 is a diagram of an analog-to-digital converter according to the invention;
- Fig. 2 shows a table having a column with a Thermometer code, a column with a Gray code, a column with an S code, a column with a binary code, and a column with unique values, the S code column comprising a four-column matrix;
- Fig. 3 is a diagram of a first logic circuit of an analog-to-digital converter according to the state of the art;
- Fig. 4 is a diagram of a first logic circuit of an analog-to-digital converter according to the invention;
- Fig. 5 is a diagram for illustrating a method according to the invention for generating an S code; and
- Fig. 6 is a further diagrammatic illustration of the method illustrated in Fig. 5.
- Fig. 1 shows an analog-to-
digital converter 2 for converting ananalog input signal 4 into a digitalbinary output signal 6. The analog-to-digital converter 2 comprises areference unit 8 for generating ameasuring signal 10 based on a comparison of theinput signal 4 with areference voltage 12. The measuring signal is a bit word from a first set of bit words. This first set is also referred to as a measuring signal code. A highly suitable type of measuring signal is a so-termed thermometer signal. - Furthermore, the analog-to-
digital converter 2 comprises afirst logic circuit 14 which is connected to thereference unit 8 for generating anintermediate signal 16 based on themeasuring signal 10. Theintermediate signal 16 is a bit word from a second set of bit words. This second set of bit words is called the intermediate code. Each bit word from the intermediate code represents a unique value, with two bit words belonging to successive unique values differing by only a single bit. The intermediate code mentioned above may be an S code, as will be further explained hereinafter. The analog-to-digital converter 2 further comprises asecond logic circuit 18 which is connected to thefirst logic circuit 14 for generating the digitalbinary output signal 6 based on theintermediate signal 16. Thebinary output signal 6 comprises a bit word from a third set of bit words. This third set is often a binary code. - The Table in Fig. 2 comprises a matrix and gives a survey of a possible relationship between the aforesaid codes. In this example the digital
binary output signal 6 comprises four bits (n=4). The Table shows a possible relationship between a measuring signal code, Gray code, and a binary code for a state of the art analog-to-digital converter. The table further shows a possible relationship between the measuring signal code, S code, and the binary code for an analog-to-digital converter 2 according to the invention. In this example the intermediate code (S code) consists of four bits. Alternatively it is possible for the intermediate code to have more than four bits so as to achieve a certain redundancy. - The first main column "Measuring Signal Code" of the Table shows the bit words of the measuring signal code. Each bit word of the measuring signal code is built up from the bits T15 to Ti. The second main column "Gray Code" of the Table shows the Gray code. The Gray code comprises bit words comprising 4 bits G1 to G4 each. The Gray code is frequently used as an intermediate code in known analog-to-digital converters. The third main column "S Code" of the Table shows an S code which may be used as an intermediate code in an analog-to-digital converter according to the invention. The fourth main column "Binary Code" in the Table shows the binary code. This binary code is used for reproducing the digital
binary output signal 6. Finally, the fifth main column in the Table ("Unique Values") shows by what path (via rows of the table) a unique value is coupled to each bit word of each code. - The following is a brief explanation of the operation of the analog-to-
digital converter 2. - In the
reference unit 8, theanalog input signal 4 is compared with thereference voltage 12. For this purpose thereference unit 8 comprises a number of comparators (not shown in the drawing) in a manner known per se, each comparator having a first and a second input terminal. Each of the first input terminals is connected to theanalog input signal 4. A unique voltage which is derived from said reference voltage is supplied to each of the second input terminals. Since the unique voltage is different for each comparator, it is possible to measure theanalog input signal 4 with the various comparators and to generate adigital measuring signal 10 based on the comparisons. In this process, each comparator drives one bit of the measuring signal code in principle. With an increasinganalog input signal 4, the measuringsignal 10 will contain an increasing number of ones. The successive bit words of the measuringsignal 10 in the Table of Fig. 2 show that the bit words of the measuringsignal 4 can be compressed further. This is effected by a transformation from thethermometer signal 10 to a 4-bit intermediate signal. According to the invention, the 4-bit intermediate signal is an S signal (according to the state of the art, for example, a Gray signal). The transformation is performed by thefirst logic circuit 14. - Fig. 3 gives an example of a
first logic circuit 14A for an analog-to-digital converter according to the state of the art with (n=4). Fig. 3 shows on the left hand side by what paths the 15 bits T1 to T15 of the bit words of the measuring signal (see also the table in Fig. 2) are applied to the inputs of the first logic circuit. The first logic circuit comprises digital AND gates 20.1 to 20.11 known per se, each gate having two inputs and one output. Each of the AND gates 20.1 to 20.7 further has one input to which an inverter (negation element) is connected. The inverters are schematically shown in circles. Furthermore, the AND gates 20.2 to 20.8 and 20.11 have an inverter at the output. Fig. 3 together with the Table of Fig. 2 show that the bits G1 to G4 of the Gray code are delivered at the outputs of thefirst logic circuit 14A. G1 is then the most significant bit of the Gray code and G4 the least significant bit of the Gray code. - The
first logic circuit 14A comprises four sub-circuits, each sub-circuit generating a bit of the Gray code. This first sub-circuit for generating G1 has alogic depth 0. This logic depth is determined by the maximum number of ports or processing elements connected in series. The second sub-circuit for generating G2 has alogic depth 1, the third sub-circuit for generating G3 has alogic depth 2, and the fourth sub-circuit for generating G4 has alogic depth 3. The logic depth of the first logic circuit is equal to the maximum logic depth of the sub-circuits and in this case equal to 3 (=n-1). - Fig. 4 schematically shows a
first logic circuit 14B of an analog-to-digital converter 2 according to the invention for n=4. It shows on the left hand side the 15 input bits T1 to T15 of the thermometer signal and on the right hand side the 4 bits S1 to S4 of the S signal. Thefirst logic circuit 14B comprises digital AND gates 22.1 to 22.12 known per se, each gate having two inputs and one output. Each of the AND gates 22.1 to 22.8 further has one input to which an inverter (negation element) is connected. Furthermore, each AND gate includes an inverter at the output. The inverters are schematically shown in circles. - The structure of the
first logic circuit 14B is such that this circuit comprises four respective sub-circuits for generating the four respective bits of the S signal. The logic depths of the various sub-circuits are equal in this example. Each logic sub-circuit has a logic depth ofcase 3;4;4;4, respectively) is substantially equally distributed over the various columns of the matrix. The number of bit changes per column is approximately equal to 2n/n. - The consequence of the foregoing is that the bits of the intermediate signal are delivered substantially simultaneously at the outputs of the
first logic circuit 14B. A further consequence is the small logic depth of thefirst logic circuit 14B, so that theintermediate signal 16 is available at the outputs of thefirst logic circuit 14B. The consequence of this is that the analog-to-digital converter according to the invention has a high data processing rate and can thus sample input signals at a high frequency. - Concerning the
first logic circuits - Figs. 5 and 6 illustrate a method of generating an S code. An S code may be used, for example, in an analog-to-digital converter according to the invention. When an S code is generated, first of all a set of bit words is defined, each bit word comprising n bits (n>1). In this example the set of bit words is derived from the Table in Fig. 2 (so in this case n=4). Fig. 5 shows a two-dimensional Karnaugh diagram in which the unique values (hexadecimal values) of a total of sixteen bit words with n=4 bits are subdivided into sixteen boxes or nodes. Each node of the diagram has exactly one unique value. Furthermore, every node of the diagram is connected to four adjacent nodes (boxes), so that the binary representations of the associated bit words differ by only 1 bit (see also the Table in Fig. 2). Fig. 5 shows, for example, that the node in which the unique 0 value occurs is connected to the nodes in which the
unique values - In the method according to the invention, a computer may be used to traverse all the nodes by every possible path via said connections provided and to select at least one matrix whose respective numbers of bit variations in the respective columns are at least substantially equal.
- The invention was described above with reference to a number of embodiments in which the intermediate code comprises four bits. However, the invention may be applied in a comparable manner to intermediate codes comprising bit words of more than four bits.
Claims (4)
- An analog-to-digital converter (2) for converting an analog input signal (4) into a digital binary output signal (6) having four or more bits, comprising:- a reference unit (8) for generating a measuring signal (10) based on a comparison of the input signal (4) with a reference voltage (12),- a first logic circuit (14) connected to the reference unit (8) for generating an intermediate signal (16) based on the measuring signal (10),- a second logic circuit (18) connected to the first logic circuit (14) for generating the digital binary output signal (6) based on the intermediate signal (16), wherein- the measuring signal (10) comprises a bit word from a first set of bit words and- the intermediate signal comprises a bit word from a second set of bit words,- each bit word representing a unique value, and- two bit words from the second set which belong to two consecutive unique values, respectively, differ by no more than one bit, and wherein- the bit words from the second set can be arranged in rows in a matrix in which the order of the rows corresponds to the unique values represented by the bit words, while- in operation each bit of the bit word of the measuring signal (10) is applied to only one input port of the first logic circuit (14),characterized in that the respective numbers of bit changes in the respective columns of the matrix formed by the bit words of the second set differ by zero or one.
- An analog-to-digital converter as claimed in claim 1, where the number of bit variations in each column of said matrix is equal to 2n/n or differs by one from 2n/n.
- A method of constructing a logic circuit for converting a thermometer code into a bit words from a set of bit words, where bit words from the set which belong to two consecutive unique values, respectively, differ by no more than one bit, the method comprising at least the following steps:defining the set of bit words, each bit word containing n bits, where n is four or more and where each bit word represents a unique value;arranging the bit words into a set of nodes, each node representing one bit word,constructing a logic circuit that when operative converts each successive thermometer code into a respective successive one of the bit words;characterized in that the method also comprises the following steps:making inter-node connections such that connections are only made between nodes of which the associated bit words differ by only one bit;successively traversing nodes by various paths via the connections thus made, a matrix being drafted for each path, the bit words of the successive nodes being accommodated in the matrix in consecutive rows;selecting a matrix from the matrices thus drafted whose respective numbers of bit variations in the respective columns of the matrix differ by zero or one.
- A method as claimed in claim 3, characterized in that when the method is executed, a computer is used for traversing all the nodes via said created connections and for selecting at least one matrix whose respective numbers of bit changes in the respective columns of the matrix differ by zero or one.
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EP02790575A EP1461866B1 (en) | 2001-12-20 | 2002-12-12 | Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter |
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EP01205046 | 2001-12-20 | ||
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EP02790575A EP1461866B1 (en) | 2001-12-20 | 2002-12-12 | Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter |
PCT/IB2002/005406 WO2003055076A2 (en) | 2001-12-20 | 2002-12-12 | Analog-to-digital converter and method of generating an intermediate code for an analog-to-digital converter |
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EP1461866B1 true EP1461866B1 (en) | 2006-11-15 |
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US (1) | US7002502B2 (en) |
EP (1) | EP1461866B1 (en) |
JP (1) | JP4027895B2 (en) |
CN (1) | CN100490328C (en) |
AT (1) | ATE345595T1 (en) |
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WO (1) | WO2003055076A2 (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7411756B2 (en) * | 2004-02-06 | 2008-08-12 | Agere Systems, Inc. | Method and apparatus for write head demagnetization |
KR20050112363A (en) * | 2004-05-25 | 2005-11-30 | 삼성전자주식회사 | Display device |
JP4347865B2 (en) * | 2006-06-22 | 2009-10-21 | ジーイー・メディカル・システムズ・グローバル・テクノロジー・カンパニー・エルエルシー | Magnetic resonance imaging apparatus and A / D conversion apparatus |
JP4842989B2 (en) * | 2008-03-28 | 2011-12-21 | 株式会社アドバンテスト | Priority encoder, time digital converter and test device using the same |
JP2010103913A (en) * | 2008-10-27 | 2010-05-06 | Toshiba Corp | A/d converter, and solid-state imaging apparatus having the same |
CN101915869A (en) * | 2010-08-13 | 2010-12-15 | 天津大学 | Method for reducing measuring error introduced by excitation signal amplitude fluctuations and implementation device |
CN105207675B (en) * | 2015-10-21 | 2018-10-02 | 昆腾微电子股份有限公司 | Coding, code translator and method for digital analog converter |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4733220A (en) * | 1985-10-04 | 1988-03-22 | Tektronix, Inc. | Thermometer-to-adjacent bindary encoder |
US4963874A (en) * | 1987-04-28 | 1990-10-16 | Matsushita Electric Industrial Co., Ltd. | Parallel type A/D converter |
US5072221A (en) * | 1988-08-04 | 1991-12-10 | Signal Processing Technologies, Inc. | Error limiting analog to digital converter |
US5525985A (en) * | 1990-12-28 | 1996-06-11 | Eaton Corporation | Sure chip |
EP0533253B1 (en) * | 1991-09-20 | 1996-07-10 | Philips Composants Et Semiconducteurs | Data conversion method for a thermometric code, decoder and converter using this method |
US5633636A (en) * | 1995-10-02 | 1997-05-27 | Analog Devices, Inc. | Half-gray digital encoding method and circuitry |
US6268819B1 (en) * | 1999-06-29 | 2001-07-31 | Texas Instruments Corporated | Bit interpolation in a resistor string data converter |
US6577257B2 (en) * | 2000-09-11 | 2003-06-10 | Broadcom Corporation | Methods and systems for digital dither |
US6542104B1 (en) * | 2001-10-22 | 2003-04-01 | Santel Networks, Inc. | Method and apparatus for low power thermometer to binary coder |
KR100500441B1 (en) * | 2002-10-22 | 2005-07-14 | 삼성전자주식회사 | Analog digital converting method and circuit of flash type |
-
2002
- 2002-12-12 AU AU2002366892A patent/AU2002366892A1/en not_active Abandoned
- 2002-12-12 US US10/498,765 patent/US7002502B2/en not_active Expired - Lifetime
- 2002-12-12 EP EP02790575A patent/EP1461866B1/en not_active Expired - Lifetime
- 2002-12-12 DE DE60216146T patent/DE60216146T2/en not_active Expired - Lifetime
- 2002-12-12 JP JP2003555681A patent/JP4027895B2/en not_active Expired - Fee Related
- 2002-12-12 CN CNB028253949A patent/CN100490328C/en not_active Expired - Fee Related
- 2002-12-12 AT AT02790575T patent/ATE345595T1/en not_active IP Right Cessation
- 2002-12-12 WO PCT/IB2002/005406 patent/WO2003055076A2/en active IP Right Grant
Also Published As
Publication number | Publication date |
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AU2002366892A1 (en) | 2003-07-09 |
AU2002366892A8 (en) | 2003-07-09 |
ATE345595T1 (en) | 2006-12-15 |
US7002502B2 (en) | 2006-02-21 |
JP4027895B2 (en) | 2007-12-26 |
CN1605157A (en) | 2005-04-06 |
DE60216146D1 (en) | 2006-12-28 |
WO2003055076A3 (en) | 2003-12-24 |
US20050146455A1 (en) | 2005-07-07 |
EP1461866A2 (en) | 2004-09-29 |
DE60216146T2 (en) | 2007-10-04 |
WO2003055076A2 (en) | 2003-07-03 |
JP2005513905A (en) | 2005-05-12 |
CN100490328C (en) | 2009-05-20 |
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