JPH11102284A - Method and circuit for selection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To select the maximum value and minimum values out of pieces of data fast with simple constitution by generating output data bits by ANDing and ORing the most significant digit bits of respective input data, converting all bits other than the most significant digit bits which are not the maximum and minimum values into logic 0 and logic 1, and outputting them. SOLUTION: An OR gate 14 outputs logic 1 when the output of an OR gate 11 as an OR means is logic 0 or when the most significant digit bit of input data is logic 1. The output data of a 1st stage 10 outputs logic 0 as all the bits of its output data since there is not the possibility that the input data has a maximum value as the most significant digit bit of the input data is logic 0 and the outputs of respective OR gates 14 are logic 0. Then data which become logic 0 once all become logic 0 in a trailing stage 20 and excluded from maximum value candidates. Therefore, the maximum value can be selected fast with the simple circuit constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selection method and a selection circuit, and more particularly to a selection method and a selection circuit capable of selecting a maximum value / minimum value from a plurality of data at a high speed.

[0002]

2. Description of the Related Art Conventionally, for example, AGC which is digitally processed
The circuit detects the maximum value of the input signal during a certain period, calculates a coefficient that is inversely proportional to this maximum value, and controls the output signal by multiplying the input signal so that the maximum value of the output signal is always constant. ing. Further, the clamp circuit detects the minimum value of the input signal in a certain period, calculates a coefficient which is a difference between the minimum value and the reference value, and adds the coefficient to the input signal, thereby always obtaining the minimum value of the output signal. Is controlled to be constant. In such a circuit, a maximum / minimum value selection circuit has been used.

FIG. 13 is a block diagram showing a configuration of a conventional maximum / minimum value selection circuit. The n pieces of data are combined two by two and input to the first-stage comparator 90.
Each comparator 90 outputs large / small data out of the input data, and the output data of each comparator 90 is input to a comparator 90 in the subsequent stage. By sequentially comparing the data in the tournament system in this manner, the maximum value / minimum value is output from the comparator 90 at the last stage.

[0004]

In the conventional maximum / minimum value selection circuit using a comparator as described above,
Since each comparator sequentially compares the most significant bit to the least significant bit of the input data, it takes a long time to perform the operation. Further, in order to compare 2 n data, the comparator must have n stages. Need to connect. Therefore, there has been a problem that the entire calculation time becomes longer. Also, 2
In order to compare n data of n, the comparator is (2n
In addition, there is a problem that a large number of circuits are required. SUMMARY OF THE INVENTION It is an object of the present invention to provide a selection method and a selection circuit which can solve the above-mentioned problems of the prior art and can quickly select a maximum value / minimum value from a plurality of data with a simple configuration. is there.

[0005]

According to the present invention, there is provided a first method of (1) taking the logical sum / product of the most significant bit of each input data and outputting the plurality of input data consisting of a plurality of bits. And (2) a second step of providing a logical 1 when the output of the first step is a logical 0 or / and the most significant bit of the input data is a logical 1 provided for each data. (3) a maximum value / minimum value obtained by repeatedly executing a third step of taking a logical product / sum of each bit other than the most significant bit of the input data and the output of the second step and outputting the result multiple times; It is characterized by a value selection method and a selection circuit for executing the method.

In the present invention, an output data bit is generated by taking the logical sum / product of the most significant bit of each input data, and all bits other than the most significant bit of data other than the maximum value / minimum value are logically zero. By converting to / logic 1 and outputting the result, processing for excluding from the maximum value / minimum value candidate is sequentially executed. Therefore, it is possible to quickly select the maximum value / minimum value with a simple configuration.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a part of a configuration of a maximum value selection circuit according to a first embodiment to which the present invention is applied. The maximum value selection circuit of the first embodiment has a configuration in which processing circuits for one bit (digit) are connected in series by the number of stages corresponding to the number of bits (digits: m) of input data. FIG. 1 shows first and second stage circuits. In this example,
The number of input data IN is N, and each input data IN
Is binary code data having m bits.

The circuit of the first stage 10 is composed of an OR gate 11 as one logical sum means and N logic circuit groups 12 and 13 corresponding to each input data IN. There are an OR gate 14 having a negative input and an [input data bit number−1] AND gates 15. The most significant bit (MSB) of each input data is connected to the input terminal of the OR gate 11, and the output of the OR gate 11 is the most significant (m-1) of the maximum value data MAX to be obtained.
It is output as bit data, and each logic circuit group 1
It is also connected to the negative input terminals of the OR gates 2 and 13.

The other input terminal of the OR gate 14 is connected to the most significant bit of the input data IN, and the output of the OR gate 14 is connected to one input terminal of an AND gate in the same logic circuit group. . This OR gate 14
The logic 1 is output when the output of the OR gate 11, which is the logical sum means, is logic 0, or when the most significant bit of the input data is logic 1. The logic 1/0 corresponds to the H (high) / L (low) level in a logic circuit designed with positive logic.

The outputs of the (m−1) AND gates 15 in the first stage become the input data of the second stage 20. 2nd stage 20
Of the AND gate 25 in each of the logic circuit groups 22 and 23
Is the same as that of the first stage except that the number of the first stage is one less than that of the first stage 10, and the input data of the second stage 20 is the first stage 1
0, and from the second stage, m-
Two-bit data is output. In this manner, the number of data bits decreases by one bit each time data passes through one stage of the circuit.

FIG. 2 is a circuit diagram showing another portion of the configuration of the maximum value selection circuit according to the first embodiment to which the present invention is applied. When the number of bits of the input data is m, m stages of processing circuits are required. FIG. 2 shows the last two stages ((m-1) th stage 30 and m th stage 40). A circuit configuration is disclosed. In the (m-1) stage 30, the number of bits of the input data is 2, and the AND gate has one bit for each data.
Only one is provided. In the last m-th stage 40,
No logic circuit group such as an AND gate is required, and the OR gate 41 outputs the least significant bit data MAX (0) of the maximum value data MAX.

Next, the operation will be described. FIG. 3 shows the first stage 1
FIG. 4 is an explanatory diagram showing an output data bit pattern for an input data bit pattern of 0 and bit data examples of maximum value data MAX. In this example, the input data number N = 5, the input data bit number m = 5, and the input data are A0 = 21, A1 = 1, A2 = 15, A3 = 25,
It is assumed that A4 = 26.

In the input bit pattern column of the table, binary code data of each input data is described. The most significant bit of each of the input data A0 to A4 is input to the OR gate 11 of FIG. In the lowermost column of the table, output data of the OR gate 11 is described as a bit output value of the output data MAX. In this example, it is shown that the most significant bit (bit 4) of MAX is logic one.

In the output bit pattern column of the table, bit pattern data of output data B0 to B4 of the first stage 10 are described. Output data B0 to B4 of the first stage 10
Of the data B0, B3, and B4, since the most significant bit of the input data is logic 1, each of the OR gates 14
Becomes a logical 1, and the lower 4 bits of the input data are output as they are via the AND gate 15.

On the other hand, the output data B1, B
2, since the most significant bits of the input data A1 and A2 are logic 0, there is no possibility that A1 and A2 have the maximum value any more, and the output of each OR gate 14 is logic 0.
Therefore, as B1 and B2, logical 0 is set to all bits.
Is output. Then, the data that once becomes logical 0 becomes logical 0 in the subsequent stage, and is excluded from the maximum value candidates.

FIGS. 4, 5, and 6 are explanatory diagrams showing examples of output data bit patterns and bit data of the maximum value data MAX with respect to the input data bit patterns of the second, third, and fourth stages, respectively. In each stage, the corresponding MAX data bit is output, and the data excluded from the maximum value candidate is converted into logical 0. For example, in FIG. 4, C0 is converted to logic 0, and in FIG. 6, E3 is converted to logic 0.

The least significant bit M of the output data MAX
AX (0) is the logical sum of the output bit patterns E0 to E4 in FIG. 6, but since E0 to E4 are all logical 0, the bit pattern of MAX is “1101”.
0 "(26 in decimal), which matches the bit pattern of A4 which is the maximum value of the input data.
The maximum value selection circuit according to the first embodiment shown in (1) can select the maximum value at high speed with a simple circuit configuration by the configuration and operation described above.

FIGS. 7 and 8 are block diagrams each showing a part of the configuration of a minimum value selection circuit according to a second embodiment of the present invention. The second embodiment is different from the first embodiment in that the AND gate in the maximum value selection circuit shown in FIGS. 1 and 2 according to the second embodiment is the same as the first embodiment.
The point is that the R gate and the OR gate are all replaced by AND gates. FIG. 8 is a circuit diagram showing the circuit configuration of the first and second stages of the minimum value selection circuit according to the second embodiment.

FIG. 7 is a circuit diagram showing the circuit configuration of the first and second stages of the minimum value selection circuit according to the second embodiment. The circuit in FIG. 7 is obtained by replacing the AND gate in the circuit diagram of the first embodiment shown in FIG. 1 with an OR gate and replacing the OR gate with an AND gate. FIG.
Is an AND gate in the circuit diagram of the first embodiment shown in FIG. 2 and an OR gate, and an OR gate in the circuit diagram of the first embodiment shown in FIG.
All are replaced with gates.

Next, the operation will be described. FIG. 9 shows the first stage 5
FIG. 4 is an explanatory diagram showing an example of an output data bit pattern corresponding to an input data bit pattern of 0 and bit data of minimum value data MIN. In this example, the input data number N = 5 and the input data bit number m = 5, and A0 = 21, A1 = 1, A2 = 15, A3 =
25, A4 = 26.

In the input bit pattern column of the table, binary code data of each input data is described. The most significant bit of each of the input data A0 to A4 is input to the AND gate 51 of FIG. In the lowest column of the table, the output data MIN
The output data of the AND gate 51 is described as the bit output value of. In this example, it is shown that the most significant bit (bit 4) of MIN is logic 0.

In the output bit pattern column of the table, bit pattern data of output data B0 to B4 of the first stage 50 is described. Output data B0 to B4 of the first stage 50
Of B1 and B2, since the most significant bit of the input data is logic 0, the output of the AND gate 54 becomes logic 0, and the lower 4 bits of the input data are output as they are via the OR gate 55. I have.

On the other hand, the output data B0, B
3 and B4, since the most significant bit of the input data A0, A3, A4 is logic 1, A0, A3, A
Since there is no possibility that 4 becomes the minimum value and the output of each AND gate 54 becomes logic 1, logic 1 is output to all bits as B0, B3 and B4. Then, data in which all bits have once become logical 1 is excluded from the minimum value candidates in the subsequent stage, because all bits become logical 1.

FIGS. 10, 11, and 12 show second,
It is explanatory drawing which shows the output data bit pattern with respect to the 3rd and 4th stage input data bit pattern, and the bit data example of the minimum value data MIN. In each stage, the MIN data bit of the corresponding digit is output, and the bit of the data excluded from the minimum value candidate is converted to logic 1.

The least significant bit M of MIN which is output data
IN (0) is the logical product of the output bit patterns E0 to E4 in FIG.
Therefore, the bit pattern of the MIN is “0000” after all.
1 "(1 in decimal), which matches the bit pattern of A1, which is the minimum value of the input data. The minimum value selection circuit of the second embodiment shown in FIGS. With such a configuration and operation, the minimum value can be quickly selected with a simple circuit configuration.

Although the embodiments have been described above, the following modifications are also conceivable. In the embodiment, an example in which either the maximum value or the minimum value is selected is disclosed. For example, the maximum value and the minimum value are simultaneously selected by simply combining the first embodiment and the second embodiment. Is also possible. As the second embodiment, a circuit in which the AND gate is replaced with an OR gate and the OR gate is replaced with an AND gate in the circuit diagram of the first embodiment is disclosed. However, the present invention can be realized by other circuit configurations. . For example, the minimum value selection circuit can be realized by adding an inverter (NOT) circuit to all the data input terminals and output terminals of the maximum value selection circuit (FIGS. 1 and 2) of the first embodiment. Similarly, the maximum value selection circuit can be realized by adding an inverter (NOT) circuit to all the data input terminals and output terminals of the minimum value selection circuit in FIGS. Also, for example, an exclusive OR (EXOR) circuit is added to all the input / output terminals, and one of the input terminals is connected to add a logical 0/1, whereby the maximum value selection circuit and the minimum value selection circuit are connected. It is also possible to switch. In the embodiment, the circuit is designed by positive logic. However, in an actual circuit configuration, by designing the circuit with negative logic, the OR gate can be formed by an AND circuit, and the AND gate is formed by An OR circuit can also be used.

[0027]

As described above, in the present invention,
An output data bit is generated by taking the logical sum / product of the most significant bit of each input data, and all bits other than the most significant bit of data other than the maximum value / minimum value are converted to logic 0 / logic 1 and output. By doing, the maximum value /
The process of excluding from the minimum value candidates is sequentially executed. Therefore,
There is an effect that the maximum value / minimum value can be sorted at high speed. Also, there is an effect that the circuit scale is smaller than in the conventional example.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of the configuration of a maximum value selection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing another part of the configuration of the maximum value selection circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of input / output data at the first stage of the first embodiment;

FIG. 4 is an explanatory diagram showing an example of input / output data in a second stage of the first embodiment;

FIG. 5 is an explanatory diagram showing an example of input / output data in a third stage of the first embodiment;

FIG. 6 is an explanatory diagram showing an example of input / output data in a fourth stage of the first embodiment;

FIG. 7 is a circuit diagram showing a part of a configuration of a minimum value selection circuit according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram showing another portion of the configuration of the minimum value selection circuit according to the second embodiment of the present invention.

FIG. 9 is an explanatory diagram showing an example of input / output data at the first stage of the first embodiment;

FIG. 10 is an explanatory diagram showing an example of input / output data at the second stage of the first embodiment;

FIG. 11 is an explanatory diagram showing an example of input / output data in the third row of the first embodiment;

FIG. 12 is an explanatory diagram showing an example of input / output data at the fourth stage of the first embodiment;

FIG. 13 is a block diagram showing a conventional maximum / minimum value selection circuit configuration.

[Explanation of symbols]

10, 50: First stage, 11, 14, 21, 24, 4
1, 55, 65... OR gate, 12, 13, 22, 23
... Logic circuit group, 15, 25, 51, 54, 61, 64,
81: AND gate, 20, 60: Second stage, 30, 7
0: 3rd stage, 40, 80: 4th stage

Claims (4)

[Claims] 1. A method of selecting a maximum value, wherein at least the following three steps are repeatedly performed a plurality of times on a plurality of pieces of input data consisting of a plurality of bits. (1) A first step of taking the logical sum of the most significant bit of each input data and outputting the result. (2) A second step of outputting a logical 1 if the output of the first step is a logical 0 or the most significant bit of the input data is a logical 1 for each data. (3) A third step of taking the logical product of each bit other than the most significant bit of the input data and the output of the second step for each data, and outputting the result. 2. A method for selecting a minimum value, wherein at least the following three steps are repeatedly performed on a plurality of input data consisting of a plurality of bits a plurality of times. (1) A first step of taking the logical product of the most significant bit of each input data and outputting the result. (2) A second step of outputting a logical 1 when the output of the first step is a logical 0 and the most significant bit of the input data is a logical 1 for each data. (3) a third step of taking a logical sum of each bit other than the most significant bit of the input data and the output of the second step for each data and outputting the result; 3. A circuit for selecting maximum value data from a plurality of data consisting of a plurality of bits, comprising: a logical sum means for taking a logical sum of the most significant bit of each input data and outputting the logical sum; A logic circuit means for outputting a logical 1 when the output of the logical sum means is a logical 0 or when the most significant bit of the input data is a logical 1; A maximum value selection circuit, wherein a plurality of logical operation means including logical product means for obtaining a logical product of each of the bits other than the bit and the output of the logical circuit means and outputting the result to the next stage are connected. 4. A circuit for selecting minimum value data from a plurality of data consisting of a plurality of bits, comprising: a logical product means for taking a logical product of the most significant bit of each input data and outputting the logical product; Logic circuit means for outputting a logical 1 when the output of the logical product means is a logical 0 and the most significant bit of the input data is a logical 1, and a most significant bit of the input data provided for each data. A plurality of logical operation means including a logical sum of each of the other bits and an output of the logic circuit means and outputting the result to the next stage, the plurality of logical operation means being connected to each other.